package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch

   1 From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
   2 From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
   3 Date: Tue, 6 Jan 2015 21:26:44 +0100
   4 Subject: sun6i: Fix and document PLL LDO voltage selection
   5
   6 The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
   7 their meaning reversed. This is fixed by this change-set. With this
   8 changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
   9 as setting the voltage to 1.37v (which it had done all along, even
  10 though stating a different target voltage).
  11
  12 After changing the PLL LDO setting, it will take a little while for
  13 the voltage output to settle. A sdelay()-based loop waits the same
  14 order of magnitude as Boot1.
  15
  16 Furthermore, a bit of documentation is added to clarify that the
  17 required setting for the PLL LDO is 1.37v as per the A31 manual.
  18
  19 diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
  20 index fa7ebd8..3a6e56e 100644
  21 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
  22 +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
  23 @@ -24,14 +24,27 @@ void clock_init_safe(void)
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27 -       /* Set PLL ldo voltage without this PLL6 does not work properly */
  28 +       /* Set PLL ldo voltage without this PLL6 does not work properly.
  29 +        *
  30 +        * As the A31 manual states, that "before enable PLL, PLLVDD
  31 +        * LDO should be set to 1.37v", we need to configure this to 2.5v
  32 +        * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
  33 +        */
  34         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  35                         PRCM_PLL_CTRL_LDO_KEY);
  36         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  37                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  38 -               PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  39 +               PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
  40         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  41
  42 +       /* Give the PLL LDO voltage setting some time to take hold.
  43 +        * Notes:
  44 +        *   1) We need to use sdelay() as the timers aren't set up yet.
  45 +        *   2) The 100k iterations come from Boot1, which spin's for 100k
  46 +        *      iterations through a loop.
  47 +        */
  48 +       sdelay(100000);
  49 +
  50         clock_set_pll1(408000000);
  51
  52         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  53 diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h
  54 index 82ed541..41a62a4 100644
  55 --- a/arch/arm/include/asm/arch-sunxi/prcm.h
  56 +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
  57 @@ -111,13 +111,13 @@
  58  #define PRCM_PLL_CTRL_LDO_OUT_MASK \
  59         __PRCM_PLL_CTRL_LDO_OUT(0x7)
  60  /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
  61 -#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
  62 -       __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
  63  #define PRCM_PLL_CTRL_LDO_OUT_H(n) \
  64 +       __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
  65 +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
  66         __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
  67 -#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
  68 -       __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
  69  #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
  70 +       __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
  71 +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
  72         __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
  73  #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
  74  #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
  75 --
  76 cgit v0.10.2
  77