target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch

   1 --- a/arch/mips/kernel/cevt-r4k.c
   2 +++ b/arch/mips/kernel/cevt-r4k.c
   3 @@ -13,6 +13,22 @@
   4  #include <asm/smtc_ipi.h>
   5  #include <asm/time.h>
   6
   7 +/*
   8 + * Compare interrupt can be routed and latched outside the core,
   9 + * so a single execution hazard barrier may not be enough to give
  10 + * it time to clear as seen in the Cause register.  4 time the
  11 + * pipeline depth seems reasonably conservative, and empirically
  12 + * works better in configurations with high CPU/bus clock ratios.
  13 + */
  14 +
  15 +#define compare_change_hazard() \
  16 +       do { \
  17 +               irq_disable_hazard(); \
  18 +               irq_disable_hazard(); \
  19 +               irq_disable_hazard(); \
  20 +               irq_disable_hazard(); \
  21 +       } while (0)
  22 +
  23  static int mips_next_event(unsigned long delta,
  24                             struct clock_event_device *evt)
  25  {
  26 @@ -28,6 +44,7 @@
  27         cnt = read_c0_count();
  28         cnt += delta;
  29         write_c0_compare(cnt);
  30 +       compare_change_hazard();
  31         res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
  32  #ifdef CONFIG_MIPS_MT_SMTC
  33         evpe(vpflags);
  34 @@ -187,7 +204,7 @@
  35          */
  36         if (c0_compare_int_pending()) {
  37                 write_c0_compare(read_c0_count());
  38 -               irq_disable_hazard();
  39 +               compare_change_hazard();
  40                 if (c0_compare_int_pending())
  41                         return 0;
  42         }
  43 @@ -196,7 +213,7 @@
  44                 cnt = read_c0_count();
  45                 cnt += delta;
  46                 write_c0_compare(cnt);
  47 -               irq_disable_hazard();
  48 +               compare_change_hazard();
  49                 if ((int)(read_c0_count() - cnt) < 0)
  50                     break;
  51                 /* increase delta if the timer was already expired */
  52 @@ -205,11 +222,12 @@
  53         while ((int)(read_c0_count() - cnt) <= 0)
  54                 ;       /* Wait for expiry  */
  55
  56 +       compare_change_hazard();
  57         if (!c0_compare_int_pending())
  58                 return 0;
  59
  60         write_c0_compare(read_c0_count());
  61 -       irq_disable_hazard();
  62 +       compare_change_hazard();
  63         if (c0_compare_int_pending())
  64                 return 0;
  65