target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c

   1 /*
   2  *  Atheros PB42 board support
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/bitops.h>
  14 #include <linux/input.h>
  15 #include <linux/platform_device.h>
  16
  17 #include <asm/mips_machine.h>
  18 #include <asm/mach-ar71xx/ar71xx.h>
  19 #include <asm/mach-ar71xx/pci.h>
  20
  21 #include "devices.h"
  22 #include "dev-m25p80.h"
  23
  24 #define PB42_BUTTONS_POLL_INTERVAL      20
  25
  26 #define PB42_GPIO_BTN_SW4       8
  27 #define PB42_GPIO_BTN_SW5       3
  28
  29 static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
  30         {
  31                 .slot   = 0,
  32                 .pin    = 1,
  33                 .irq    = AR71XX_PCI_IRQ_DEV0,
  34         }, {
  35                 .slot   = 1,
  36                 .pin    = 1,
  37                 .irq    = AR71XX_PCI_IRQ_DEV1,
  38         }, {
  39                 .slot   = 2,
  40                 .pin    = 1,
  41                 .irq    = AR71XX_PCI_IRQ_DEV2,
  42         }
  43 };
  44
  45 static struct gpio_button pb42_gpio_buttons[] __initdata = {
  46         {
  47                 .desc           = "sw4",
  48                 .type           = EV_KEY,
  49                 .code           = BTN_0,
  50                 .threshold      = 5,
  51                 .gpio           = PB42_GPIO_BTN_SW4,
  52                 .active_low     = 1,
  53         } , {
  54                 .desc           = "sw5",
  55                 .type           = EV_KEY,
  56                 .code           = BTN_1,
  57                 .threshold      = 5,
  58                 .gpio           = PB42_GPIO_BTN_SW5,
  59                 .active_low     = 1,
  60         }
  61 };
  62
  63 #define PB42_WAN_PHYMASK        BIT(20)
  64 #define PB42_LAN_PHYMASK        (BIT(16) | BIT(17) | BIT(18) | BIT(19))
  65 #define PB42_MDIO_PHYMASK       (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK)
  66
  67 static void __init pb42_init(void)
  68 {
  69         ar71xx_add_device_m25p80(NULL);
  70
  71         ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
  72
  73         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
  74         ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
  75
  76         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
  77         ar71xx_eth1_data.phy_mask = PB42_LAN_PHYMASK;
  78         ar71xx_eth1_data.speed = SPEED_100;
  79         ar71xx_eth1_data.duplex = DUPLEX_FULL;
  80
  81         ar71xx_add_device_eth(0);
  82         ar71xx_add_device_eth(1);
  83
  84         ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
  85                                        ARRAY_SIZE(pb42_gpio_buttons),
  86                                        pb42_gpio_buttons);
  87
  88         ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
  89 }
  90
  91 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);