2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
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40 * Ioctl-related definitions for the Atheros Wireless LAN controller driver.
42 #ifndef _DEV_ATH_ATHIOCTL_H
43 #define _DEV_ATH_ATHIOCTL_H
46 u_int32_t ast_watchdog; /* device reset by watchdog */
47 u_int32_t ast_hardware; /* fatal hardware error interrupts */
48 u_int32_t ast_bmiss; /* beacon miss interrupts */
49 u_int32_t ast_rxorn; /* rx overrun interrupts */
50 u_int32_t ast_rxeol; /* rx eol interrupts */
51 u_int32_t ast_txurn; /* tx underrun interrupts */
52 u_int32_t ast_mib; /* mib interrupts */
53 u_int32_t ast_tx_packets; /* packet sent on the interface */
54 u_int32_t ast_tx_mgmt; /* management frames transmitted */
55 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
56 u_int32_t ast_tx_invalid; /* frames discarded due to is device gone */
57 u_int32_t ast_tx_qstop; /* tx queue stopped because it's full */
58 u_int32_t ast_tx_encap; /* tx encapsulation failed */
59 u_int32_t ast_tx_nonode; /* tx failed due to of no node */
60 u_int32_t ast_tx_nobuf; /* tx failed due to of no tx buffer (data) */
61 u_int32_t ast_tx_nobufmgt; /* tx failed due to of no tx buffer (mgmt)*/
62 u_int32_t ast_tx_xretries; /* tx failed due to of too many retries */
63 u_int32_t ast_tx_fifoerr; /* tx failed due to of FIFO underrun */
64 u_int32_t ast_tx_filtered; /* tx failed due to xmit filtered */
65 u_int32_t ast_tx_shortretry; /* tx on-chip retries (short) */
66 u_int32_t ast_tx_longretry; /* tx on-chip retries (long) */
67 u_int32_t ast_tx_badrate; /* tx failed due to of bogus xmit rate */
68 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
69 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
70 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
71 u_int32_t ast_tx_shortpre; /* tx frames with short preamble */
72 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
73 u_int32_t ast_tx_protect; /* tx frames with protection */
74 u_int32_t ast_rx_orn; /* rx failed due to of desc overrun */
75 u_int32_t ast_rx_crcerr; /* rx failed due to of bad CRC */
76 u_int32_t ast_rx_fifoerr; /* rx failed due to of FIFO overrun */
77 u_int32_t ast_rx_badcrypt; /* rx failed due to of decryption */
78 u_int32_t ast_rx_badmic; /* rx failed due to of MIC failure */
79 u_int32_t ast_rx_phyerr; /* rx PHY error summary count */
80 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
81 u_int32_t ast_rx_tooshort; /* rx discarded due to frame too short */
82 u_int32_t ast_rx_toobig; /* rx discarded due to frame too large */
83 u_int32_t ast_rx_nobuf; /* rx setup failed due to of no skbuff */
84 u_int32_t ast_rx_packets; /* packet recv on the interface */
85 u_int32_t ast_rx_mgt; /* management frames received */
86 u_int32_t ast_rx_ctl; /* control frames received */
87 int8_t ast_tx_rssi; /* tx rssi of last ack */
88 int8_t ast_rx_rssi; /* rx rssi from histogram */
89 u_int32_t ast_be_xmit; /* beacons transmitted */
90 u_int32_t ast_be_nobuf; /* no skbuff available for beacon */
91 u_int32_t ast_per_cal; /* periodic calibration calls */
92 u_int32_t ast_per_calfail; /* periodic calibration failed */
93 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
94 u_int32_t ast_rate_calls; /* rate control checks */
95 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
96 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
97 u_int32_t ast_ant_defswitch; /* rx/default antenna switches */
98 u_int32_t ast_ant_txswitch; /* tx antenna switches */
99 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
100 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
105 #define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
106 #define ATH_DIAG_IN 0x4000 /* copy in parameters */
107 #define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
108 #define ATH_DIAG_ID 0x0fff
109 void __user *ad_in_data;
110 void __user *ad_out_data;
112 unsigned ad_out_size;
115 #define ATH_RADAR_MUTE_TIME 1 /* Set dfs mute time for dfs test mode */
117 #define SIOCGATHSTATS (SIOCDEVPRIVATE+0)
118 #define SIOCGATHDIAG (SIOCDEVPRIVATE+1)
119 #define SIOCGATHRADARSIG (SIOCDEVPRIVATE+2)
120 #define SIOCGATHHALDIAG (SIOCDEVPRIVATE+3)
121 #endif /* _DEV_ATH_ATHIOCTL_H */