ath/if_ath_ahb.h

   1 /*
   2  * Copyright (c) 2004 Atheros Communications, Inc.
   3  * All rights reserved.
   4  *
   5  * $Id$
   6  */
   7
   8 #ifndef _DEV_ATH_AHB_H_
   9 #define _DEV_ATH_AHB_H_
  10
  11 #include <asm/io.h>
  12 #include <asm/uaccess.h>
  13 #include <linux/dma-mapping.h>
  14
  15 #define AR531X_WLAN0_NUM       0
  16 #define AR531X_WLAN1_NUM       1
  17
  18 #define REG_WRITE(_reg,_val)            *((volatile u_int32_t *)(_reg)) = (_val);
  19 #define REG_READ(_reg)                  *((volatile u_int32_t *)(_reg))
  20
  21 /*
  22  * 5315 specific registers
  23  */
  24
  25 /*
  26  * PCI-MAC Configuration registers
  27  */
  28 #define AR5315_PCI              0xB0100000      /* PCI MMR */
  29 #define AR5315_PCI_MAC_RC       (AR5315_PCI + 0x4000)
  30 #define AR5315_PCI_MAC_SCR      (AR5315_PCI + 0x4004)
  31 #define AR5315_PCI_MAC_INTPEND  (AR5315_PCI + 0x4008)
  32 #define AR5315_PCI_MAC_SFR      (AR5315_PCI + 0x400C)
  33 #define AR5315_PCI_MAC_PCICFG   (AR5315_PCI + 0x4010)
  34 #define AR5315_PCI_MAC_SREV     (AR5315_PCI + 0x4020)
  35
  36 #define AR5315_PCI_MAC_RC_MAC   0x00000001
  37 #define AR5315_PCI_MAC_RC_BB    0x00000002
  38
  39 #define AR5315_PCI_MAC_SCR_SLMODE_M     0x00030000
  40 #define AR5315_PCI_MAC_SCR_SLMODE_S     16
  41 #define AR5315_PCI_MAC_SCR_SLM_FWAKE    0
  42 #define AR5315_PCI_MAC_SCR_SLM_FSLEEP   1
  43 #define AR5315_PCI_MAC_SCR_SLM_NORMAL   2
  44
  45 #define AR5315_PCI_MAC_SFR_SLEEP        0x00000001
  46
  47 #define AR5315_PCI_MAC_PCICFG_SPWR_DN   0x00010000
  48
  49 #define AR5315_IRQ_WLAN0_INTRS  3
  50 #define AR5315_WLAN0            0xb0000000
  51
  52 #define AR5315_ENDIAN_CTL       0xb100000c
  53 #define AR5315_CONFIG_WLAN      0x00000002      /* WLAN byteswap */
  54 #define AR5315_AHB_ARB_CTL      0xb1000008
  55 #define AR5315_ARB_WLAN         0x00000002
  56
  57 /*
  58  * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
  59  */
  60 #define AR5315_SREV             0xb1000014
  61
  62 #define AR5315_REV_MAJ          0x0080
  63 #define AR5317_REV_MAJ          0x0090
  64 #define AR5315_REV_MAJ_M        0x00f0
  65 #define AR5315_REV_MAJ_S        4
  66 #define AR5315_REV_MIN_M        0x000f
  67 #define AR5315_REV_MIN_S        0
  68 #define AR5315_REV_CHIP         (REV_MAJ|REV_MIN)
  69
  70 #define AR531X_IRQ_WLAN0_INTRS  2
  71 #define AR531X_IRQ_WLAN1_INTRS  5
  72 #define AR531X_WLAN0            0xb8000000
  73 #define AR531X_WLAN1            0xb8500000
  74 #define AR531X_WLANX_LEN        0x000ffffc
  75
  76 #define AR531X_RESETCTL         0xbc003020
  77 #define AR531X_RESET_WLAN0                      0x00000004      /* mac & bb */
  78 #define AR531X_RESET_WLAN1                      0x00000200      /* mac & bb */
  79 #define AR531X_RESET_WARM_WLAN0_MAC             0x00002000
  80 #define AR531X_RESET_WARM_WLAN0_BB              0x00004000
  81 #define AR531X_RESET_WARM_WLAN1_MAC             0x00020000
  82 #define AR531X_RESET_WARM_WLAN1_BB              0x00040000
  83
  84 #define AR531X_ENABLE           0xbc003080
  85 #define AR531X_ENABLE_WLAN0                     0x0001
  86 #define AR531X_ENABLE_WLAN1                     0x0018  /* both DMA and PIO */
  87
  88 #define AR531X_RADIO_MASK_OFF   0xc8
  89 #define AR531X_RADIO0_MASK      0x0003
  90 #define AR531X_RADIO1_MASK      0x000c
  91 #define AR531X_RADIO1_S         2
  92
  93 #define BUS_DMA_FROMDEVICE      DMA_FROM_DEVICE
  94 #define BUS_DMA_TODEVICE        DMA_TO_DEVICE
  95
  96 #define AR531X_APBBASE          0xbc000000
  97 #define AR531X_RESETTMR         (AR531X_APBBASE  + 0x3000)
  98 #define AR531X_REV              (AR531X_RESETTMR + 0x0090) /* revision */
  99 #define AR531X_REV_MAJ          0x00f0
 100 #define AR531X_REV_MAJ_S        4
 101 #define AR531X_REV_MIN          0x000f
 102 #define AR531X_REV_MIN_S        0
 103
 104 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
 105
 106 /* Allow compiling on non-mips platforms for code verification */
 107 #ifndef KSEG1ADDR
 108 #define KSEG1ADDR(addr) (addr)
 109 #endif
 110
 111 #define bus_dma_sync_single     dma_sync_single_for_cpu
 112 #define bus_map_single          dma_map_single
 113 #define bus_unmap_single        dma_unmap_single
 114 #define bus_alloc_consistent(_hwdev, _sz, _hdma)                \
 115         dma_alloc_coherent((_hwdev), (_sz), (_hdma), GFP_ATOMIC)
 116 #define bus_free_consistent     dma_free_coherent
 117
 118 #endif    /* _DEV_ATH_AHB_H_ */