[ar7] use the righ value in the DSP clock calculation

[openwrt-10.03/.git] / target / linux / ar7 / files / arch / mips / ar7 / clock.c

diff --git a/target/linux/ar7/files/arch/mips/ar7/clock.c b/target/linux/ar7/files/arch/mips/ar7/clock.c
index 450769e7fd5c18e8a97986cf0766a0fc0e22941f..25e6b7326c391eac75662363852faece3e4effc2 100644 (file)
--- a/target/linux/ar7/files/arch/mips/ar7/clock.c
+++ b/target/linux/ar7/files/arch/mips/ar7/clock.c
@@ -180,8 +180,8 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 {
        int product;
        int base_clock = AR7_REF_CLOCK;
-       u32 ctrl = clock->ctrl;
-       u32 pll = clock->pll;
+       u32 ctrl = readl(&clock->ctrl);
+       u32 pll = readl(&clock->pll);
        int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
        int postdiv = (ctrl & POSTDIV_MASK) + 1;
        int divisor = prediv * postdiv;
@@ -224,7 +224,6 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
        u32 *bootcr, u32 frequency)
 {
-       u32 status;
        int prediv, postdiv, mul;
        int base_clock = ar7_bus_clock;
 
@@ -245,13 +244,11 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 
        calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 
-       clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
+       writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
        mdelay(1);
-       clock->pll = 4;
-       do
-               status = clock->pll;
-       while (status & PLL_STATUS);
-       clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
+       writel(4, &clock->pll);
+       while (readl(&clock->pll) & PLL_STATUS);
+       writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
        mdelay(75);
 }
 
@@ -286,13 +283,13 @@ static void __init tnetd7300_init_clocks(void)
 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
        u32 *bootcr, u32 bus_clock)
 {
-       int divisor = ((clock->prediv & 0x1f) + 1) *
-               ((clock->postdiv & 0x1f) + 1);
+       int divisor = ((readl(&clock->prediv) & 0x1f) + 1) *
+               ((readl(&clock->postdiv) & 0x1f) + 1);
 
        if (*bootcr & BOOT_PLL_BYPASS)
                return base / divisor;
 
-       return base * ((clock->mul & 0xf) + 1) / divisor;
+       return base * ((readl(&clock->mul) & 0xf) + 1) / divisor;
 }
 
 
@@ -304,29 +301,29 @@ static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
                "postdiv = %d, postdiv2 = %d, mul = %d\n",
                base, frequency, prediv, postdiv, postdiv2, mul);
 
-       clock->ctrl = 0;
-       clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
-       clock->mul = ((mul - 1) & 0xF);
+       writel(0, &clock->ctrl);
+       writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
+       writel((mul - 1) & 0xF, &clock->mul);
 
        for (mul = 0; mul < 2000; mul++) /* nop */;
 
-       while (clock->status & 0x1) /* nop */;
+       while (readl(&clock->status) & 0x1) /* nop */;
 
-       clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
+       writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
 
-       clock->cmden |= 1;
-       clock->cmd |= 1;
+       writel(readl(&clock->cmden) | 1, &clock->cmden);
+       writel(readl(&clock->cmd) | 1, &clock->cmd);
 
-       while (clock->status & 0x1) /* nop */;
+       while (readl(&clock->status) & 0x1) /* nop */;
 
-       clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
+       writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
 
-       clock->cmden |= 1;
-       clock->cmd |= 1;
+       writel(readl(&clock->cmden) | 1, &clock->cmden);
+       writel(readl(&clock->cmd) | 1, &clock->cmd);
 
-       while (clock->status & 0x1) /* nop */;
+       while (readl(&clock->status) & 0x1) /* nop */;
 
-       clock->ctrl |= 1;
+       writel(readl(&clock->ctrl) | 1, &clock->ctrl);
 }
 
 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
@@ -440,7 +437,7 @@ static void __init tnetd7200_init_clocks(void)
                        printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
 
                        printk(KERN_INFO "Clocks: Setting DSP clock\n");
-                       calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv,
+                       calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
                                &dsp_postdiv, &dsp_mul);
                        ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
                                                                / dsp_postdiv;