}
static CLASS_DEVICE_ATTR(async, S_IRUGO, show_async, NULL);
-
-#define DBG_SCHED_LIMIT 64
-
-static ssize_t
-show_periodic(struct class_device *class_dev, char *buf)
-{
-#if 0
- struct usb_bus *bus;
- struct usb_hcd *hcd;
- struct admhcd *ahcd;
- struct ed **seen, *ed;
- unsigned long flags;
- unsigned temp, size, seen_count;
- char *next;
- unsigned i;
-
- if (!(seen = kmalloc(DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
- return 0;
- seen_count = 0;
-
- bus = class_get_devdata(class_dev);
- hcd = bus_to_hcd(bus);
- ahcd = hcd_to_admhcd(hcd);
- next = buf;
- size = PAGE_SIZE;
-
- temp = scnprintf(next, size, "size = %d\n", NUM_INTS);
- size -= temp;
- next += temp;
-
- /* dump a snapshot of the periodic schedule (and load) */
- spin_lock_irqsave(&ahcd->lock, flags);
- for (i = 0; i < NUM_INTS; i++) {
- if (!(ed = ahcd->periodic [i]))
- continue;
-
- temp = scnprintf(next, size, "%2d [%3d]:", i, ahcd->load [i]);
- size -= temp;
- next += temp;
-
- do {
- temp = scnprintf(next, size, " ed%d/%p",
- ed->interval, ed);
- size -= temp;
- next += temp;
- for (temp = 0; temp < seen_count; temp++) {
- if (seen [temp] == ed)
- break;
- }
-
- /* show more info the first time around */
- if (temp == seen_count) {
- u32 info = hc32_to_cpu (ahcd, ed->hwINFO);
- struct list_head *entry;
- unsigned qlen = 0;
-
- /* qlen measured here in TDs, not urbs */
- list_for_each (entry, &ed->td_list)
- qlen++;
- temp = scnprintf(next, size,
- " (%cs dev%d ep%d%s qlen %u"
- " max %d %08x%s%s)",
- (info & ED_SPEED_FULL) ? 'f' : 'l',
- ED_FA_GET(info),
- ED_EN_GET(info),
- (info & ED_ISO) ? "iso" : "int",
- qlen,
- ED_MPS_GET(info),
- info,
- (info & ED_SKIP) ? " K" : "",
- (ed->hwHeadP &
- cpu_to_hc32(ahcd, ED_H)) ?
- " H" : "");
- size -= temp;
- next += temp;
-
- if (seen_count < DBG_SCHED_LIMIT)
- seen [seen_count++] = ed;
-
- ed = ed->ed_next;
-
- } else {
- /* we've seen it and what's after */
- temp = 0;
- ed = NULL;
- }
-
- } while (ed);
-
- temp = scnprintf(next, size, "\n");
- size -= temp;
- next += temp;
- }
- spin_unlock_irqrestore(&ahcd->lock, flags);
- kfree (seen);
-
- return PAGE_SIZE - size;
-#else
- return 0;
-#endif
-}
-static CLASS_DEVICE_ATTR(periodic, S_IRUGO, show_periodic, NULL);
-
-
-#undef DBG_SCHED_LIMIT
-
static ssize_t
show_registers(struct class_device *class_dev, char *buf)
{
int retval;
retval = class_device_create_file(cldev, &class_device_attr_async);
- retval = class_device_create_file(cldev, &class_device_attr_periodic);
retval = class_device_create_file(cldev, &class_device_attr_registers);
admhc_dbg(ahcd, "created debug files\n");
}
struct class_device *cldev = admhcd_to_hcd(ahcd)->self.class_dev;
class_device_remove_file(cldev, &class_device_attr_async);
- class_device_remove_file(cldev, &class_device_attr_periodic);
class_device_remove_file(cldev, &class_device_attr_registers);
}
#include "../core/hcd.h"
#include "../core/hub.h"
-#define DRIVER_VERSION "v0.04"
+#define DRIVER_VERSION "v0.05"
#define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
#define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
/*-------------------------------------------------------------------------*/
#define ADMHC_VERBOSE_DEBUG /* not always helpful */
-#define ADMHC_POLL_RH
-#undef ADMHC_LOCK_DMA
/* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
/* schedule the ED */
ret = ed_schedule(ahcd, ed);
-fail0:
spin_unlock(&urb->lock);
fail:
if (ret) {
static inline int admhc_port_reset(struct admhcd *ahcd, unsigned port)
{
u32 t;
- int c;
admhc_vdbg(ahcd, "reset port%d\n", port);
-
t = admhc_read_portstatus(ahcd, port);
if (!(t & ADMHC_PS_CCS))
return -ENODEV;
- if ((t & ADMHC_PS_PRS))
- return 0;
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_PRS);
- c = 0;
- do {
- t = admhc_read_portstatus(ahcd, port);
- if (t & ADMHC_PS_PRSC)
- break;
-
- if (++c > 20) {
- admhc_err(ahcd, "port%d reset timed out\n",port);
- return -EPIPE;
- }
-
- mdelay(PORT_RESET_HW_MSEC);
- } while (1);
- admhc_vdbg(ahcd, "port%d reset completed within %dms\n", port,
- c * PORT_RESET_HW_MSEC);
-
- t = admhc_read_portstatus(ahcd, port);
- if (!(t & ADMHC_PS_CCS)) {
- admhc_err(ahcd, "port%d is not connected after reset\n",port);
- return -ENODEV;
- }
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_SPE);
- c = 0;
- do {
- t = admhc_read_portstatus(ahcd, port);
- if (t & ADMHC_PS_PESC)
- break;
-
- if (++c > 20) {
- admhc_err(ahcd, "port%d enable timed out\n",port);
- return -EPIPE;
- }
-
- mdelay(PORT_RESET_HW_MSEC);
- } while (1);
- admhc_vdbg(ahcd, "port%d enable completed within %dms\n", port,
- c * PORT_RESET_HW_MSEC);
-
- admhc_write_portstatus(ahcd, port, ADMHC_PS_CSC);
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_SPR);
+ mdelay(10);
+ admhc_write_portstatus(ahcd, port, (ADMHC_PS_SPE | ADMHC_PS_CSC));
+ mdelay(100);
return 0;
}
if (!(t & ADMHC_PS_CCS))
return -ENODEV;
- admhc_write_portstatus(ahcd, ADMHC_PS_CPE, port);
+ admhc_write_portstatus(ahcd, port, ADMHC_PS_CPE);
return 0;
}
static inline int admhc_port_write(struct admhcd *ahcd, unsigned port,
u32 val)
{
+#ifdef ADMHC_VERBOSE_DEBUG
dbg_port_write(ahcd, "write", port, val);
+#endif
admhc_write_portstatus(ahcd, port, val);
return 0;
/* rest are purely for the driver's use */
__u8 index;
-/* struct ed *ed;*/
struct urb *urb;
dma_addr_t td_dma; /* addr of this TD */
#define admhc_err(ahcd, fmt, args...) \
printk(KERN_ERR "adm5120-hcd: " fmt , ## args )
-#define ahcd_info(ahcd, fmt, args...) \
+#define admhc_info(ahcd, fmt, args...) \
printk(KERN_INFO "adm5120-hcd: " fmt , ## args )
#define admhc_warn(ahcd, fmt, args...) \
printk(KERN_WARNING "adm5120-hcd: " fmt , ## args )
projects / openwrt-10.03 / .git / commitdiff