[backfire] cleanup: remove unsupported "octeon" target
authornico <nico@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Wed, 23 Nov 2011 22:18:49 +0000 (22:18 +0000)
committernico <nico@3c298f89-4303-0410-b956-a3cf2f4a3e73>
Wed, 23 Nov 2011 22:18:49 +0000 (22:18 +0000)
git-svn-id: svn://svn.openwrt.org/openwrt/branches/backfire@29314 3c298f89-4303-0410-b956-a3cf2f4a3e73

34 files changed:
package/kernel/modules/block.mk
package/kernel/modules/usb.mk
package/madwifi/Makefile
target/linux/octeon/Makefile [deleted file]
target/linux/octeon/base-files/etc/config/network [deleted file]
target/linux/octeon/config-2.6.30 [deleted file]
target/linux/octeon/config/profile-mototech [deleted file]
target/linux/octeon/config/profile-simulator [deleted file]
target/linux/octeon/image/Makefile [deleted file]
target/linux/octeon/patches-2.6.30/001-handle_removal_h_constraint.patch [deleted file]
target/linux/octeon/patches-2.6.30/002-register_defs_pci.patch [deleted file]
target/linux/octeon/patches-2.6.30/003_pci_pcie_support.patch [deleted file]
target/linux/octeon/patches-2.6.30/004-named_alloc_function.patch [deleted file]
target/linux/octeon/patches-2.6.30/005-register_defs_octeon_mgmt.patch [deleted file]
target/linux/octeon/patches-2.6.30/006-octeon_mgmt_driver.patch [deleted file]
target/linux/octeon/patches-2.6.30/007-export_cvmx_sysinfo.patch [deleted file]
target/linux/octeon/patches-2.6.30/008-more_board_types_constraints.patch [deleted file]
target/linux/octeon/patches-2.6.30/009-more_chip_specific_feature_tests.patch [deleted file]
target/linux/octeon/patches-2.6.30/010-export_erratum_function.patch [deleted file]
target/linux/octeon/patches-2.6.30/011-octeon_ethernet_driver.patch [deleted file]
target/linux/octeon/patches-2.6.30/012-hook_up_eth_driver.patch [deleted file]
target/linux/octeon/patches-2.6.30/013-compile_fixes.patch [deleted file]
target/linux/octeon/patches-2.6.30/015-no_werror.patch [deleted file]
target/linux/octeon/patches-2.6.30/016-octeon_hw_rng.patch [deleted file]
target/linux/octeon/patches-2.6.30/017-platform_devices.patch [deleted file]
target/linux/octeon/patches-2.6.30/018-dwc_otg.patch [deleted file]
target/linux/octeon/patches-2.6.30/100-wndap330_hacks.patch [deleted file]
target/linux/octeon/patches-2.6.30/105-nb5_fixup.patch [deleted file]
target/linux/octeon/patches-2.6.30/106-no_module_reloc.patch [deleted file]
target/linux/octeon/profiles/000-Generic.mk [deleted file]
target/linux/octeon/profiles/100-Mototech.mk [deleted file]
target/linux/octeon/profiles/200-Simulator.mk [deleted file]
toolchain/gcc/Config.in
toolchain/gcc/Config.version

index 9f9f4701e2d6067fcb9074481f717fd47aa6ff52..475bc4b25a53196a4ffda33ae0caabb0faf84dea 100644 (file)
@@ -83,21 +83,6 @@ endef
 
 $(eval $(call KernelPackage,ata-artop))
 
-define KernelPackage/ata-octeon-cf
-$(call KernelPackage/ata/Depends,@TARGET_octeon)
-  TITLE:=Octeon Compact Flash support
-  KCONFIG:=CONFIG_PATA_OCTEON_CF
-  FILES:=$(LINUX_DIR)/drivers/ata/pata_octeon_cf.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,41,pata_octeon_cf,1)
-endef
-
-define KernelPackage/ata-octeon-cf/description
-  Octeon Compact Flash support.
-endef
-
-$(eval $(call KernelPackage,ata-octeon-cf))
-
-
 define KernelPackage/ata-ixp4xx-cf
 $(call KernelPackage/ata/Depends,@TARGET_ixp4xx)
   TITLE:=IXP4XX Compact Flash support
index a9498d8266495c104e4731683f262bbe8dcdab2d..437a199bf49e3542ce16ffd37e0a52268d0385f9 100644 (file)
@@ -128,20 +128,6 @@ endef
 
 $(eval $(call KernelPackage,usb-adm5120))
 
-define KernelPackage/usb-octeon
-$(call KernelPackage/usb/Depends,@TARGET_octeon)
-  TITLE:=Support for the Octeon USB OTG controller
-  KCONFIG:=CONFIG_USB_DWC_OTG
-  FILES:=$(LINUX_DIR)/drivers/usb/host/dwc_otg/dwc_otg.$(LINUX_KMOD_SUFFIX)
-  AUTOLOAD:=$(call AutoLoad,50,dwc_otg)
-endef
-
-define KernelPackage/usb-octeon/description
-  Kernel support for the Octeon USB host controller
-endef
-
-$(eval $(call KernelPackage,usb-octeon))
-
 
 define KernelPackage/usb-isp116x-hcd
 $(call KernelPackage/usb/Depends,@TARGET_ppc40x)
index dd1c61cdbc7a843195cd6db55635cdc8cf4e34b1..6996d6510cb6502e7bddf6a2cca9c5f32b7de977 100644 (file)
@@ -156,7 +156,7 @@ define KernelPackage/madwifi
   TITLE:=Driver for Atheros wireless chipsets
   URL:=http://madwifi-project.org/
   MAINTAINER:=Felix Fietkau <nbd@openwrt.org>
-  DEPENDS:=+wireless-tools @LINUX_2_6 @PCI_SUPPORT @(!(TARGET_avr32||TARGET_ep93xx||TARGET_octeon)||BROKEN)
+  DEPENDS:=+wireless-tools @LINUX_2_6 @PCI_SUPPORT @(!(TARGET_avr32||TARGET_ep93xx)||BROKEN)
   FILES:=$(MADWIFI_FILES)
   AUTOLOAD:=$(call AutoLoad,50,$(MADWIFI_AUTOLOAD))
   MENU:=1
diff --git a/target/linux/octeon/Makefile b/target/linux/octeon/Makefile
deleted file mode 100644 (file)
index 182ec1e..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Copyright (C) 2009 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-
-ARCH:=mips
-BOARD:=octeon
-BOARDNAME:=Cavium Networks Octeon
-FEATURES:=squashfs jffs2 pci usb
-CFLAGS:=-Os -pipe -mtune=octeon -funit-at-a-time
-
-LINUX_VERSION:=2.6.30.10
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += wpad-mini
-
-define Target/Description
-       Build firmware images for Cavium Networks Octeon-based boards.
-endef
-
-$(eval $(call BuildTarget))
diff --git a/target/linux/octeon/base-files/etc/config/network b/target/linux/octeon/base-files/etc/config/network
deleted file mode 100644 (file)
index 44c5794..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (C) 2009 OpenWrt.org
-
-config interface loopback
-        option ifname   lo
-        option proto    static
-        option ipaddr   127.0.0.1
-        option netmask  255.0.0.0
-
-config interface lan
-        option ifname   eth1
-        option type     bridge
-        option proto    static
-        option ipaddr   192.168.1.1
-        option netmask  255.255.255.0
-
-config interface wan
-       option ifname   eth0
-       option proto    dhcp
diff --git a/target/linux/octeon/config-2.6.30 b/target/linux/octeon/config-2.6.30
deleted file mode 100644 (file)
index 59d1375..0000000
+++ /dev/null
@@ -1,268 +0,0 @@
-# CONFIG_32BIT is not set
-CONFIG_64BIT_PHYS_ADDR=y
-CONFIG_64BIT=y
-# CONFIG_ALTERA_PCIE_CHDMA is not set
-# CONFIG_ANDROID_BINDER_IPC is not set
-# CONFIG_ANDROID is not set
-# CONFIG_ANDROID_LOGGER is not set
-# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set
-# CONFIG_ANDROID_RAM_CONSOLE is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUPPORTS_MSI=y
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-# CONFIG_ARPD is not set
-# CONFIG_B3DFG is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_BCM47XX is not set
-# CONFIG_BINARY_PRINTF is not set
-CONFIG_BINFMT_ELF32=y
-CONFIG_BITREVERSE=y
-CONFIG_BLOCK_COMPAT=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-# CONFIG_BOOT_PRINTK_DELAY is not set
-CONFIG_BSD_PROCESS_ACCT_V3=y
-# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
-CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
-CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
-CONFIG_CAVIUM_OCTEON_LOCK_L2=y
-CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
-# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
-CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CEVT_R4K=y
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_CMDLINE="console=ttyS0,115200"
-# CONFIG_COMEDI is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_COMPAT=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_CAVIUM_OCTEON=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2 is not set
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-CONFIG_CPU_MIPSR2=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R5500 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
-CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
-CONFIG_CRAMFS=y
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_DEBUG_DRIVER is not set
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_SPINLOCK=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DETECT_SOFTLOCKUP=y
-CONFIG_DEVKMEM=y
-CONFIG_DEVPORT=y
-# CONFIG_DM9000 is not set
-CONFIG_DMA_COHERENT=y
-CONFIG_DNOTIFY=y
-# CONFIG_DST is not set
-CONFIG_EARLY_PRINTK=y
-# CONFIG_ECHO is not set
-CONFIG_ELF_CORE=y
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_ET131X is not set
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_FLATMEM_MANUAL is not set
-CONFIG_FRAME_WARN=2048
-# CONFIG_FW_LOADER is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_GROUP_SCHED=y
-# CONFIG_HAMRADIO is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_SYSCALL_WRAPPERS=y
-# CONFIG_HECI is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM_OCTEON=y
-CONFIG_HW_RANDOM=y
-# CONFIG_HZ_100 is not set
-CONFIG_HZ=250
-CONFIG_HZ_250=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INOTIFY_USER=y
-CONFIG_INOTIFY=y
-CONFIG_IRQ_CPU_OCTEON=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_PER_CPU=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC=y
-# CONFIG_KGDB is not set
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LEGACY_PTYS=y
-# CONFIG_LEMOTE_FULONG is not set
-CONFIG_LOCK_KERNEL=y
-# CONFIG_LOCK_STAT is not set
-# CONFIG_MACH_ALCHEMY is not set
-# CONFIG_MACH_DECSTATION is not set
-# CONFIG_MACH_JAZZ is not set
-# CONFIG_MACH_TX39XX is not set
-# CONFIG_MACH_TX49XX is not set
-# CONFIG_MACH_VR41XX is not set
-# CONFIG_ME4000 is not set
-# CONFIG_MEILHAUS is not set
-# CONFIG_MIKROTIK_RB532 is not set
-CONFIG_MIPS32_COMPAT=y
-CONFIG_MIPS32_N32=y
-CONFIG_MIPS32_O32=y
-# CONFIG_MIPS_COBALT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=7
-# CONFIG_MIPS_MACHINE is not set
-# CONFIG_MIPS_MALTA is not set
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_SIM is not set
-CONFIG_MIPS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_NO_IOPORT is not set
-CONFIG_NR_CPUS=16
-CONFIG_NR_CPUS_DEFAULT_16=y
-# CONFIG_NXP_STB220 is not set
-# CONFIG_NXP_STB225 is not set
-CONFIG_OCTEON_ETHERNET=y
-CONFIG_OCTEON_MGMT=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PAGE_POISONING is not set
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PCI=y
-# CONFIG_PCI_DEBUG is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PLAN9AUTH is not set
-# CONFIG_PMC_MSP is not set
-# CONFIG_PMC_YOSEMITE is not set
-# CONFIG_PNX8550_JBS is not set
-# CONFIG_PNX8550_STB810 is not set
-# CONFIG_POHMELFS is not set
-CONFIG_POSIX_MQUEUE_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-# CONFIG_PROBE_INITRD_HEADER is not set
-CONFIG_PROC_PAGE_MONITOR=y
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RELAY=y
-# CONFIG_RT_GROUP_SCHED is not set
-# CONFIG_RTL8187SE is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_RUNTIME_DEBUG is not set
-CONFIG_SCHED_DEBUG=y
-CONFIG_SCHED_OMIT_FRAME_POINTER=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_SCSI_DMA is not set
-CONFIG_SECCOMP=y
-# CONFIG_SERIAL_8250_EXTENDED is not set
-# CONFIG_SGI_IP22 is not set
-# CONFIG_SGI_IP27 is not set
-# CONFIG_SGI_IP28 is not set
-# CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_CRHINE is not set
-# CONFIG_SIBYTE_CRHONE is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SLOW_WORK is not set
-CONFIG_SMP=y
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_SPARSEMEM=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-CONFIG_STAGING=y
-CONFIG_STOP_MACHINE=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYSVIPC_COMPAT=y
-# CONFIG_TC35815 is not set
-# CONFIG_TIMER_STATS is not set
-CONFIG_TRACING_SUPPORT=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_USER_SCHED=y
-# CONFIG_VLAN_8021Q is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WEAK_ORDERING=y
-CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
-# CONFIG_WLAN_80211 is not set
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/octeon/config/profile-mototech b/target/linux/octeon/config/profile-mototech
deleted file mode 100644 (file)
index dc73845..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_CRAMFS=y
-CONFIG_MTD_CMDLINE_PARTS=y
diff --git a/target/linux/octeon/config/profile-simulator b/target/linux/octeon/config/profile-simulator
deleted file mode 100644 (file)
index 5fbefec..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_CMDLINE="console=ttyS0,115200 numcores=16"
-CONFIG_CAVIUM_OCTEON_SIMULATOR=y
diff --git a/target/linux/octeon/image/Makefile b/target/linux/octeon/image/Makefile
deleted file mode 100644 (file)
index 358bbe8..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Copyright (C) 2009-2010 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-define Image/BuildKernel
-       # Workaround pre-SDK-1.9.0 u-boot versions not handling the .notes section
-       $(TARGET_CROSS)strip -R .notes $(KDIR)/vmlinux.elf -o $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf
-       $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7
-       dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux.lzma bs=65536 conv=sync
-endef
-
-define Image/Build/squashfs
-    $(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
-endef
-
-define Image/Build
-       $(call Image/Build/$(1))
-       dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync
-endef
-
-$(eval $(call BuildImage))
diff --git a/target/linux/octeon/patches-2.6.30/001-handle_removal_h_constraint.patch b/target/linux/octeon/patches-2.6.30/001-handle_removal_h_constraint.patch
deleted file mode 100644 (file)
index ea19508..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-This is an incomplete proof of concept that I applied to be able to
-build a 64 bit kernel with GCC-4.4.  It doesn't handle the 32 bit case
-or the R4000_WAR case.
-
-Comments welcome.
-
-Signed-off-by: David Daney <ddaney@caviumnetworks.com>
----
- arch/mips/include/asm/compiler.h |    7 +++++++
- 2 files changed, 11 insertions(+), 0 deletions(-)
-
---- a/arch/mips/include/asm/compiler.h
-+++ b/arch/mips/include/asm/compiler.h
-@@ -16,4 +16,11 @@
- #define GCC_REG_ACCUM "accum"
- #endif
-+#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
-+#define GCC_NO_H_CONSTRAINT
-+#ifdef CONFIG_64BIT
-+typedef unsigned int uint128_t __attribute__((mode(TI)));
-+#endif
-+#endif
-+
- #endif /* _ASM_COMPILER_H */
diff --git a/target/linux/octeon/patches-2.6.30/002-register_defs_pci.patch b/target/linux/octeon/patches-2.6.30/002-register_defs_pci.patch
deleted file mode 100644 (file)
index 85a910d..0000000
+++ /dev/null
@@ -1,9383 +0,0 @@
-Here we add the register definitions for the processor blocks used by
-the following PCI support patch.
-
-Signed-off-by: David Daney <ddaney@caviumnetworks.com>
----
- arch/mips/include/asm/octeon/cvmx-npei-defs.h    | 2560 ++++++++++++++++++++++
- arch/mips/include/asm/octeon/cvmx-npi-defs.h     | 1735 +++++++++++++++
- arch/mips/include/asm/octeon/cvmx-pci-defs.h     | 1645 ++++++++++++++
- arch/mips/include/asm/octeon/cvmx-pcieep-defs.h  | 1365 ++++++++++++
- arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 1397 ++++++++++++
- arch/mips/include/asm/octeon/cvmx-pescx-defs.h   |  410 ++++
- arch/mips/include/asm/octeon/cvmx-pexp-defs.h    |  229 ++
- 7 files changed, 9341 insertions(+), 0 deletions(-)
- create mode 100644 arch/mips/include/asm/octeon/cvmx-npei-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-npi-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-pci-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-pescx-defs.h
- create mode 100644 arch/mips/include/asm/octeon/cvmx-pexp-defs.h
-
---- /dev/null
-+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
-@@ -0,0 +1,2560 @@
-+/***********************license start***************
-+ * Author: Cavium Networks
-+ *
-+ * Contact: support@caviumnetworks.com
-+ * This file is part of the OCTEON SDK
-+ *
-+ * Copyright (c) 2003-2008 Cavium Networks
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ *
-+ * This file is distributed in the hope that it will be useful, but
-+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
-+ * NONINFRINGEMENT.  See the GNU General Public License for more
-+ * details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this file; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ * or visit http://www.gnu.org/licenses/.
-+ *
-+ * This file may also be available under a different license from Cavium.
-+ * Contact Cavium Networks for more information
-+ ***********************license end**************************************/
-+
-+#ifndef __CVMX_NPEI_DEFS_H__
-+#define __CVMX_NPEI_DEFS_H__
-+
-+#define CVMX_NPEI_BAR1_INDEXX(offset) \
-+       (0x0000000000000000ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_BIST_STATUS \
-+       (0x0000000000000580ull)
-+#define CVMX_NPEI_BIST_STATUS2 \
-+       (0x0000000000000680ull)
-+#define CVMX_NPEI_CTL_PORT0 \
-+       (0x0000000000000250ull)
-+#define CVMX_NPEI_CTL_PORT1 \
-+       (0x0000000000000260ull)
-+#define CVMX_NPEI_CTL_STATUS \
-+       (0x0000000000000570ull)
-+#define CVMX_NPEI_CTL_STATUS2 \
-+       (0x0000000000003C00ull)
-+#define CVMX_NPEI_DATA_OUT_CNT \
-+       (0x00000000000005F0ull)
-+#define CVMX_NPEI_DBG_DATA \
-+       (0x0000000000000510ull)
-+#define CVMX_NPEI_DBG_SELECT \
-+       (0x0000000000000500ull)
-+#define CVMX_NPEI_DMA0_INT_LEVEL \
-+       (0x00000000000005C0ull)
-+#define CVMX_NPEI_DMA1_INT_LEVEL \
-+       (0x00000000000005D0ull)
-+#define CVMX_NPEI_DMAX_COUNTS(offset) \
-+       (0x0000000000000450ull + (((offset) & 7) * 16))
-+#define CVMX_NPEI_DMAX_DBELL(offset) \
-+       (0x00000000000003B0ull + (((offset) & 7) * 16))
-+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
-+       (0x0000000000000400ull + (((offset) & 7) * 16))
-+#define CVMX_NPEI_DMAX_NADDR(offset) \
-+       (0x00000000000004A0ull + (((offset) & 7) * 16))
-+#define CVMX_NPEI_DMA_CNTS \
-+       (0x00000000000005E0ull)
-+#define CVMX_NPEI_DMA_CONTROL \
-+       (0x00000000000003A0ull)
-+#define CVMX_NPEI_INT_A_ENB \
-+       (0x0000000000000560ull)
-+#define CVMX_NPEI_INT_A_ENB2 \
-+       (0x0000000000003CE0ull)
-+#define CVMX_NPEI_INT_A_SUM \
-+       (0x0000000000000550ull)
-+#define CVMX_NPEI_INT_ENB \
-+       (0x0000000000000540ull)
-+#define CVMX_NPEI_INT_ENB2 \
-+       (0x0000000000003CD0ull)
-+#define CVMX_NPEI_INT_INFO \
-+       (0x0000000000000590ull)
-+#define CVMX_NPEI_INT_SUM \
-+       (0x0000000000000530ull)
-+#define CVMX_NPEI_INT_SUM2 \
-+       (0x0000000000003CC0ull)
-+#define CVMX_NPEI_LAST_WIN_RDATA0 \
-+       (0x0000000000000600ull)
-+#define CVMX_NPEI_LAST_WIN_RDATA1 \
-+       (0x0000000000000610ull)
-+#define CVMX_NPEI_MEM_ACCESS_CTL \
-+       (0x00000000000004F0ull)
-+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
-+       (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
-+#define CVMX_NPEI_MSI_ENB0 \
-+       (0x0000000000003C50ull)
-+#define CVMX_NPEI_MSI_ENB1 \
-+       (0x0000000000003C60ull)
-+#define CVMX_NPEI_MSI_ENB2 \
-+       (0x0000000000003C70ull)
-+#define CVMX_NPEI_MSI_ENB3 \
-+       (0x0000000000003C80ull)
-+#define CVMX_NPEI_MSI_RCV0 \
-+       (0x0000000000003C10ull)
-+#define CVMX_NPEI_MSI_RCV1 \
-+       (0x0000000000003C20ull)
-+#define CVMX_NPEI_MSI_RCV2 \
-+       (0x0000000000003C30ull)
-+#define CVMX_NPEI_MSI_RCV3 \
-+       (0x0000000000003C40ull)
-+#define CVMX_NPEI_MSI_RD_MAP \
-+       (0x0000000000003CA0ull)
-+#define CVMX_NPEI_MSI_W1C_ENB0 \
-+       (0x0000000000003CF0ull)
-+#define CVMX_NPEI_MSI_W1C_ENB1 \
-+       (0x0000000000003D00ull)
-+#define CVMX_NPEI_MSI_W1C_ENB2 \
-+       (0x0000000000003D10ull)
-+#define CVMX_NPEI_MSI_W1C_ENB3 \
-+       (0x0000000000003D20ull)
-+#define CVMX_NPEI_MSI_W1S_ENB0 \
-+       (0x0000000000003D30ull)
-+#define CVMX_NPEI_MSI_W1S_ENB1 \
-+       (0x0000000000003D40ull)
-+#define CVMX_NPEI_MSI_W1S_ENB2 \
-+       (0x0000000000003D50ull)
-+#define CVMX_NPEI_MSI_W1S_ENB3 \
-+       (0x0000000000003D60ull)
-+#define CVMX_NPEI_MSI_WR_MAP \
-+       (0x0000000000003C90ull)
-+#define CVMX_NPEI_PCIE_CREDIT_CNT \
-+       (0x0000000000003D70ull)
-+#define CVMX_NPEI_PCIE_MSI_RCV \
-+       (0x0000000000003CB0ull)
-+#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
-+       (0x0000000000000650ull)
-+#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
-+       (0x0000000000000660ull)
-+#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
-+       (0x0000000000000670ull)
-+#define CVMX_NPEI_PKTX_CNTS(offset) \
-+       (0x0000000000002400ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
-+       (0x0000000000002800ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
-+       (0x0000000000002C00ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
-+       (0x0000000000003000ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
-+       (0x0000000000003400ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_IN_BP(offset) \
-+       (0x0000000000003800ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
-+       (0x0000000000001400ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
-+       (0x0000000000001800ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
-+       (0x0000000000001C00ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKT_CNT_INT \
-+       (0x0000000000001110ull)
-+#define CVMX_NPEI_PKT_CNT_INT_ENB \
-+       (0x0000000000001130ull)
-+#define CVMX_NPEI_PKT_DATA_OUT_ES \
-+       (0x00000000000010B0ull)
-+#define CVMX_NPEI_PKT_DATA_OUT_NS \
-+       (0x00000000000010A0ull)
-+#define CVMX_NPEI_PKT_DATA_OUT_ROR \
-+       (0x0000000000001090ull)
-+#define CVMX_NPEI_PKT_DPADDR \
-+       (0x0000000000001080ull)
-+#define CVMX_NPEI_PKT_INPUT_CONTROL \
-+       (0x0000000000001150ull)
-+#define CVMX_NPEI_PKT_INSTR_ENB \
-+       (0x0000000000001000ull)
-+#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
-+       (0x0000000000001190ull)
-+#define CVMX_NPEI_PKT_INSTR_SIZE \
-+       (0x0000000000001020ull)
-+#define CVMX_NPEI_PKT_INT_LEVELS \
-+       (0x0000000000001100ull)
-+#define CVMX_NPEI_PKT_IN_BP \
-+       (0x00000000000006B0ull)
-+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
-+       (0x0000000000002000ull + (((offset) & 31) * 16))
-+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
-+       (0x00000000000006A0ull)
-+#define CVMX_NPEI_PKT_IN_PCIE_PORT \
-+       (0x00000000000011A0ull)
-+#define CVMX_NPEI_PKT_IPTR \
-+       (0x0000000000001070ull)
-+#define CVMX_NPEI_PKT_OUTPUT_WMARK \
-+       (0x0000000000001160ull)
-+#define CVMX_NPEI_PKT_OUT_BMODE \
-+       (0x00000000000010D0ull)
-+#define CVMX_NPEI_PKT_OUT_ENB \
-+       (0x0000000000001010ull)
-+#define CVMX_NPEI_PKT_PCIE_PORT \
-+       (0x00000000000010E0ull)
-+#define CVMX_NPEI_PKT_PORT_IN_RST \
-+       (0x0000000000000690ull)
-+#define CVMX_NPEI_PKT_SLIST_ES \
-+       (0x0000000000001050ull)
-+#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
-+       (0x0000000000001180ull)
-+#define CVMX_NPEI_PKT_SLIST_NS \
-+       (0x0000000000001040ull)
-+#define CVMX_NPEI_PKT_SLIST_ROR \
-+       (0x0000000000001030ull)
-+#define CVMX_NPEI_PKT_TIME_INT \
-+       (0x0000000000001120ull)
-+#define CVMX_NPEI_PKT_TIME_INT_ENB \
-+       (0x0000000000001140ull)
-+#define CVMX_NPEI_RSL_INT_BLOCKS \
-+       (0x0000000000000520ull)
-+#define CVMX_NPEI_SCRATCH_1 \
-+       (0x0000000000000270ull)
-+#define CVMX_NPEI_STATE1 \
-+       (0x0000000000000620ull)
-+#define CVMX_NPEI_STATE2 \
-+       (0x0000000000000630ull)
-+#define CVMX_NPEI_STATE3 \
-+       (0x0000000000000640ull)
-+#define CVMX_NPEI_WINDOW_CTL \
-+       (0x0000000000000380ull)
-+#define CVMX_NPEI_WIN_RD_ADDR \
-+       (0x0000000000000210ull)
-+#define CVMX_NPEI_WIN_RD_DATA \
-+       (0x0000000000000240ull)
-+#define CVMX_NPEI_WIN_WR_ADDR \
-+       (0x0000000000000200ull)
-+#define CVMX_NPEI_WIN_WR_DATA \
-+       (0x0000000000000220ull)
-+#define CVMX_NPEI_WIN_WR_MASK \
-+       (0x0000000000000230ull)
-+
-+union cvmx_npei_bar1_indexx {
-+      uint32_t u32;
-+      struct cvmx_npei_bar1_indexx_s {
-+              uint32_t reserved_18_31:14;
-+              uint32_t addr_idx:14;
-+              uint32_t ca:1;
-+              uint32_t end_swp:2;
-+              uint32_t addr_v:1;
-+      } s;
-+      struct cvmx_npei_bar1_indexx_s cn52xx;
-+      struct cvmx_npei_bar1_indexx_s cn52xxp1;
-+      struct cvmx_npei_bar1_indexx_s cn56xx;
-+      struct cvmx_npei_bar1_indexx_s cn56xxp1;
-+};
-+
-+union cvmx_npei_bist_status {
-+      uint64_t u64;
-+      struct cvmx_npei_bist_status_s {
-+              uint64_t pkt_rdf:1;
-+              uint64_t pkt_pmem:1;
-+              uint64_t pkt_p1:1;
-+              uint64_t reserved_60_60:1;
-+              uint64_t pcr_gim:1;
-+              uint64_t pkt_pif:1;
-+              uint64_t pcsr_int:1;
-+              uint64_t pcsr_im:1;
-+              uint64_t pcsr_cnt:1;
-+              uint64_t pcsr_id:1;
-+              uint64_t pcsr_sl:1;
-+              uint64_t reserved_50_52:3;
-+              uint64_t pkt_ind:1;
-+              uint64_t pkt_slm:1;
-+              uint64_t reserved_36_47:12;
-+              uint64_t d0_pst:1;
-+              uint64_t d1_pst:1;
-+              uint64_t d2_pst:1;
-+              uint64_t d3_pst:1;
-+              uint64_t reserved_31_31:1;
-+              uint64_t n2p0_c:1;
-+              uint64_t n2p0_o:1;
-+              uint64_t n2p1_c:1;
-+              uint64_t n2p1_o:1;
-+              uint64_t cpl_p0:1;
-+              uint64_t cpl_p1:1;
-+              uint64_t p2n1_po:1;
-+              uint64_t p2n1_no:1;
-+              uint64_t p2n1_co:1;
-+              uint64_t p2n0_po:1;
-+              uint64_t p2n0_no:1;
-+              uint64_t p2n0_co:1;
-+              uint64_t p2n0_c0:1;
-+              uint64_t p2n0_c1:1;
-+              uint64_t p2n0_n:1;
-+              uint64_t p2n0_p0:1;
-+              uint64_t p2n0_p1:1;
-+              uint64_t p2n1_c0:1;
-+              uint64_t p2n1_c1:1;
-+              uint64_t p2n1_n:1;
-+              uint64_t p2n1_p0:1;
-+              uint64_t p2n1_p1:1;
-+              uint64_t csm0:1;
-+              uint64_t csm1:1;
-+              uint64_t dif0:1;
-+              uint64_t dif1:1;
-+              uint64_t dif2:1;
-+              uint64_t dif3:1;
-+              uint64_t reserved_2_2:1;
-+              uint64_t msi:1;
-+              uint64_t ncb_cmd:1;
-+      } s;
-+      struct cvmx_npei_bist_status_cn52xx {
-+              uint64_t pkt_rdf:1;
-+              uint64_t pkt_pmem:1;
-+              uint64_t pkt_p1:1;
-+              uint64_t reserved_60_60:1;
-+              uint64_t pcr_gim:1;
-+              uint64_t pkt_pif:1;
-+              uint64_t pcsr_int:1;
-+              uint64_t pcsr_im:1;
-+              uint64_t pcsr_cnt:1;
-+              uint64_t pcsr_id:1;
-+              uint64_t pcsr_sl:1;
-+              uint64_t pkt_imem:1;
-+              uint64_t pkt_pfm:1;
-+              uint64_t pkt_pof:1;
-+              uint64_t reserved_48_49:2;
-+              uint64_t pkt_pop0:1;
-+              uint64_t pkt_pop1:1;
-+              uint64_t d0_mem:1;
-+              uint64_t d1_mem:1;
-+              uint64_t d2_mem:1;
-+              uint64_t d3_mem:1;
-+              uint64_t d4_mem:1;
-+              uint64_t ds_mem:1;
-+              uint64_t reserved_36_39:4;
-+              uint64_t d0_pst:1;
-+              uint64_t d1_pst:1;
-+              uint64_t d2_pst:1;
-+              uint64_t d3_pst:1;
-+              uint64_t d4_pst:1;
-+              uint64_t n2p0_c:1;
-+              uint64_t n2p0_o:1;
-+              uint64_t n2p1_c:1;
-+              uint64_t n2p1_o:1;
-+              uint64_t cpl_p0:1;
-+              uint64_t cpl_p1:1;
-+              uint64_t p2n1_po:1;
-+              uint64_t p2n1_no:1;
-+              uint64_t p2n1_co:1;
-+              uint64_t p2n0_po:1;
-+              uint64_t p2n0_no:1;
-+              uint64_t p2n0_co:1;
-+              uint64_t p2n0_c0:1;
-+              uint64_t p2n0_c1:1;
-+              uint64_t p2n0_n:1;
-+              uint64_t p2n0_p0:1;
-+              uint64_t p2n0_p1:1;
-+              uint64_t p2n1_c0:1;
-+              uint64_t p2n1_c1:1;
-+              uint64_t p2n1_n:1;
-+              uint64_t p2n1_p0:1;
-+              uint64_t p2n1_p1:1;
-+              uint64_t csm0:1;
-+              uint64_t csm1:1;
-+              uint64_t dif0:1;
-+              uint64_t dif1:1;
-+              uint64_t dif2:1;
-+              uint64_t dif3:1;
-+              uint64_t dif4:1;
-+              uint64_t msi:1;
-+              uint64_t ncb_cmd:1;
-+      } cn52xx;
-+      struct cvmx_npei_bist_status_cn52xxp1 {
-+              uint64_t reserved_46_63:18;
-+              uint64_t d0_mem0:1;
-+              uint64_t d1_mem1:1;
-+              uint64_t d2_mem2:1;
-+              uint64_t d3_mem3:1;
-+              uint64_t dr0_mem:1;
-+              uint64_t d0_mem:1;
-+              uint64_t d1_mem:1;
-+              uint64_t d2_mem:1;
-+              uint64_t d3_mem:1;
-+              uint64_t dr1_mem:1;
-+              uint64_t d0_pst:1;
-+              uint64_t d1_pst:1;
-+              uint64_t d2_pst:1;
-+              uint64_t d3_pst:1;
-+              uint64_t dr2_mem:1;
-+              uint64_t n2p0_c:1;
-+              uint64_t n2p0_o:1;
-+              uint64_t n2p1_c:1;
-+              uint64_t n2p1_o:1;
-+              uint64_t cpl_p0:1;
-+              uint64_t cpl_p1:1;
-+              uint64_t p2n1_po:1;
-+              uint64_t p2n1_no:1;
-+              uint64_t p2n1_co:1;
-+              uint64_t p2n0_po:1;
-+              uint64_t p2n0_no:1;
-+              uint64_t p2n0_co:1;
-+              uint64_t p2n0_c0:1;
-+              uint64_t p2n0_c1:1;
-+              uint64_t p2n0_n:1;
-+              uint64_t p2n0_p0:1;
-+              uint64_t p2n0_p1:1;
-+              uint64_t p2n1_c0:1;
-+              uint64_t p2n1_c1:1;
-+              uint64_t p2n1_n:1;
-+              uint64_t p2n1_p0:1;
-+              uint64_t p2n1_p1:1;
-+              uint64_t csm0:1;
-+              uint64_t csm1:1;
-+              uint64_t dif0:1;
-+              uint64_t dif1:1;
-+              uint64_t dif2:1;
-+              uint64_t dif3:1;
-+              uint64_t dr3_mem:1;
-+              uint64_t msi:1;
-+              uint64_t ncb_cmd:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_bist_status_cn56xx {
-+              uint64_t pkt_rdf:1;
-+              uint64_t reserved_60_62:3;
-+              uint64_t pcr_gim:1;
-+              uint64_t pkt_pif:1;
-+              uint64_t pcsr_int:1;
-+              uint64_t pcsr_im:1;
-+              uint64_t pcsr_cnt:1;
-+              uint64_t pcsr_id:1;
-+              uint64_t pcsr_sl:1;
-+              uint64_t pkt_imem:1;
-+              uint64_t pkt_pfm:1;
-+              uint64_t pkt_pof:1;
-+              uint64_t reserved_48_49:2;
-+              uint64_t pkt_pop0:1;
-+              uint64_t pkt_pop1:1;
-+              uint64_t d0_mem:1;
-+              uint64_t d1_mem:1;
-+              uint64_t d2_mem:1;
-+              uint64_t d3_mem:1;
-+              uint64_t d4_mem:1;
-+              uint64_t ds_mem:1;
-+              uint64_t reserved_36_39:4;
-+              uint64_t d0_pst:1;
-+              uint64_t d1_pst:1;
-+              uint64_t d2_pst:1;
-+              uint64_t d3_pst:1;
-+              uint64_t d4_pst:1;
-+              uint64_t n2p0_c:1;
-+              uint64_t n2p0_o:1;
-+              uint64_t n2p1_c:1;
-+              uint64_t n2p1_o:1;
-+              uint64_t cpl_p0:1;
-+              uint64_t cpl_p1:1;
-+              uint64_t p2n1_po:1;
-+              uint64_t p2n1_no:1;
-+              uint64_t p2n1_co:1;
-+              uint64_t p2n0_po:1;
-+              uint64_t p2n0_no:1;
-+              uint64_t p2n0_co:1;
-+              uint64_t p2n0_c0:1;
-+              uint64_t p2n0_c1:1;
-+              uint64_t p2n0_n:1;
-+              uint64_t p2n0_p0:1;
-+              uint64_t p2n0_p1:1;
-+              uint64_t p2n1_c0:1;
-+              uint64_t p2n1_c1:1;
-+              uint64_t p2n1_n:1;
-+              uint64_t p2n1_p0:1;
-+              uint64_t p2n1_p1:1;
-+              uint64_t csm0:1;
-+              uint64_t csm1:1;
-+              uint64_t dif0:1;
-+              uint64_t dif1:1;
-+              uint64_t dif2:1;
-+              uint64_t dif3:1;
-+              uint64_t dif4:1;
-+              uint64_t msi:1;
-+              uint64_t ncb_cmd:1;
-+      } cn56xx;
-+      struct cvmx_npei_bist_status_cn56xxp1 {
-+              uint64_t reserved_58_63:6;
-+              uint64_t pcsr_int:1;
-+              uint64_t pcsr_im:1;
-+              uint64_t pcsr_cnt:1;
-+              uint64_t pcsr_id:1;
-+              uint64_t pcsr_sl:1;
-+              uint64_t pkt_pout:1;
-+              uint64_t pkt_imem:1;
-+              uint64_t pkt_cntm:1;
-+              uint64_t pkt_ind:1;
-+              uint64_t pkt_slm:1;
-+              uint64_t pkt_odf:1;
-+              uint64_t pkt_oif:1;
-+              uint64_t pkt_out:1;
-+              uint64_t pkt_i0:1;
-+              uint64_t pkt_i1:1;
-+              uint64_t pkt_s0:1;
-+              uint64_t pkt_s1:1;
-+              uint64_t d0_mem:1;
-+              uint64_t d1_mem:1;
-+              uint64_t d2_mem:1;
-+              uint64_t d3_mem:1;
-+              uint64_t d4_mem:1;
-+              uint64_t d0_pst:1;
-+              uint64_t d1_pst:1;
-+              uint64_t d2_pst:1;
-+              uint64_t d3_pst:1;
-+              uint64_t d4_pst:1;
-+              uint64_t n2p0_c:1;
-+              uint64_t n2p0_o:1;
-+              uint64_t n2p1_c:1;
-+              uint64_t n2p1_o:1;
-+              uint64_t cpl_p0:1;
-+              uint64_t cpl_p1:1;
-+              uint64_t p2n1_po:1;
-+              uint64_t p2n1_no:1;
-+              uint64_t p2n1_co:1;
-+              uint64_t p2n0_po:1;
-+              uint64_t p2n0_no:1;
-+              uint64_t p2n0_co:1;
-+              uint64_t p2n0_c0:1;
-+              uint64_t p2n0_c1:1;
-+              uint64_t p2n0_n:1;
-+              uint64_t p2n0_p0:1;
-+              uint64_t p2n0_p1:1;
-+              uint64_t p2n1_c0:1;
-+              uint64_t p2n1_c1:1;
-+              uint64_t p2n1_n:1;
-+              uint64_t p2n1_p0:1;
-+              uint64_t p2n1_p1:1;
-+              uint64_t csm0:1;
-+              uint64_t csm1:1;
-+              uint64_t dif0:1;
-+              uint64_t dif1:1;
-+              uint64_t dif2:1;
-+              uint64_t dif3:1;
-+              uint64_t dif4:1;
-+              uint64_t msi:1;
-+              uint64_t ncb_cmd:1;
-+      } cn56xxp1;
-+};
-+
-+union cvmx_npei_bist_status2 {
-+      uint64_t u64;
-+      struct cvmx_npei_bist_status2_s {
-+              uint64_t reserved_5_63:59;
-+              uint64_t psc_p0:1;
-+              uint64_t psc_p1:1;
-+              uint64_t pkt_gd:1;
-+              uint64_t pkt_gl:1;
-+              uint64_t pkt_blk:1;
-+      } s;
-+      struct cvmx_npei_bist_status2_s cn52xx;
-+      struct cvmx_npei_bist_status2_s cn56xx;
-+};
-+
-+union cvmx_npei_ctl_port0 {
-+      uint64_t u64;
-+      struct cvmx_npei_ctl_port0_s {
-+              uint64_t reserved_21_63:43;
-+              uint64_t waitl_com:1;
-+              uint64_t intd:1;
-+              uint64_t intc:1;
-+              uint64_t intb:1;
-+              uint64_t inta:1;
-+              uint64_t intd_map:2;
-+              uint64_t intc_map:2;
-+              uint64_t intb_map:2;
-+              uint64_t inta_map:2;
-+              uint64_t ctlp_ro:1;
-+              uint64_t reserved_6_6:1;
-+              uint64_t ptlp_ro:1;
-+              uint64_t bar2_enb:1;
-+              uint64_t bar2_esx:2;
-+              uint64_t bar2_cax:1;
-+              uint64_t wait_com:1;
-+      } s;
-+      struct cvmx_npei_ctl_port0_s cn52xx;
-+      struct cvmx_npei_ctl_port0_s cn52xxp1;
-+      struct cvmx_npei_ctl_port0_s cn56xx;
-+      struct cvmx_npei_ctl_port0_s cn56xxp1;
-+};
-+
-+union cvmx_npei_ctl_port1 {
-+      uint64_t u64;
-+      struct cvmx_npei_ctl_port1_s {
-+              uint64_t reserved_21_63:43;
-+              uint64_t waitl_com:1;
-+              uint64_t intd:1;
-+              uint64_t intc:1;
-+              uint64_t intb:1;
-+              uint64_t inta:1;
-+              uint64_t intd_map:2;
-+              uint64_t intc_map:2;
-+              uint64_t intb_map:2;
-+              uint64_t inta_map:2;
-+              uint64_t ctlp_ro:1;
-+              uint64_t reserved_6_6:1;
-+              uint64_t ptlp_ro:1;
-+              uint64_t bar2_enb:1;
-+              uint64_t bar2_esx:2;
-+              uint64_t bar2_cax:1;
-+              uint64_t wait_com:1;
-+      } s;
-+      struct cvmx_npei_ctl_port1_s cn52xx;
-+      struct cvmx_npei_ctl_port1_s cn52xxp1;
-+      struct cvmx_npei_ctl_port1_s cn56xx;
-+      struct cvmx_npei_ctl_port1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_ctl_status {
-+      uint64_t u64;
-+      struct cvmx_npei_ctl_status_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t p1_ntags:6;
-+              uint64_t p0_ntags:6;
-+              uint64_t cfg_rtry:16;
-+              uint64_t ring_en:1;
-+              uint64_t lnk_rst:1;
-+              uint64_t arb:1;
-+              uint64_t pkt_bp:4;
-+              uint64_t host_mode:1;
-+              uint64_t chip_rev:8;
-+      } s;
-+      struct cvmx_npei_ctl_status_s cn52xx;
-+      struct cvmx_npei_ctl_status_cn52xxp1 {
-+              uint64_t reserved_44_63:20;
-+              uint64_t p1_ntags:6;
-+              uint64_t p0_ntags:6;
-+              uint64_t cfg_rtry:16;
-+              uint64_t reserved_15_15:1;
-+              uint64_t lnk_rst:1;
-+              uint64_t arb:1;
-+              uint64_t reserved_9_12:4;
-+              uint64_t host_mode:1;
-+              uint64_t chip_rev:8;
-+      } cn52xxp1;
-+      struct cvmx_npei_ctl_status_s cn56xx;
-+      struct cvmx_npei_ctl_status_cn56xxp1 {
-+              uint64_t reserved_16_63:48;
-+              uint64_t ring_en:1;
-+              uint64_t lnk_rst:1;
-+              uint64_t arb:1;
-+              uint64_t pkt_bp:4;
-+              uint64_t host_mode:1;
-+              uint64_t chip_rev:8;
-+      } cn56xxp1;
-+};
-+
-+union cvmx_npei_ctl_status2 {
-+      uint64_t u64;
-+      struct cvmx_npei_ctl_status2_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t mps:1;
-+              uint64_t mrrs:3;
-+              uint64_t c1_w_flt:1;
-+              uint64_t c0_w_flt:1;
-+              uint64_t c1_b1_s:3;
-+              uint64_t c0_b1_s:3;
-+              uint64_t c1_wi_d:1;
-+              uint64_t c1_b0_d:1;
-+              uint64_t c0_wi_d:1;
-+              uint64_t c0_b0_d:1;
-+      } s;
-+      struct cvmx_npei_ctl_status2_s cn52xx;
-+      struct cvmx_npei_ctl_status2_s cn52xxp1;
-+      struct cvmx_npei_ctl_status2_s cn56xx;
-+      struct cvmx_npei_ctl_status2_s cn56xxp1;
-+};
-+
-+union cvmx_npei_data_out_cnt {
-+      uint64_t u64;
-+      struct cvmx_npei_data_out_cnt_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t p1_ucnt:16;
-+              uint64_t p1_fcnt:6;
-+              uint64_t p0_ucnt:16;
-+              uint64_t p0_fcnt:6;
-+      } s;
-+      struct cvmx_npei_data_out_cnt_s cn52xx;
-+      struct cvmx_npei_data_out_cnt_s cn52xxp1;
-+      struct cvmx_npei_data_out_cnt_s cn56xx;
-+      struct cvmx_npei_data_out_cnt_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dbg_data {
-+      uint64_t u64;
-+      struct cvmx_npei_dbg_data_s {
-+              uint64_t reserved_28_63:36;
-+              uint64_t qlm0_rev_lanes:1;
-+              uint64_t reserved_25_26:2;
-+              uint64_t qlm1_spd:2;
-+              uint64_t c_mul:5;
-+              uint64_t dsel_ext:1;
-+              uint64_t data:17;
-+      } s;
-+      struct cvmx_npei_dbg_data_cn52xx {
-+              uint64_t reserved_29_63:35;
-+              uint64_t qlm0_link_width:1;
-+              uint64_t qlm0_rev_lanes:1;
-+              uint64_t qlm1_mode:2;
-+              uint64_t qlm1_spd:2;
-+              uint64_t c_mul:5;
-+              uint64_t dsel_ext:1;
-+              uint64_t data:17;
-+      } cn52xx;
-+      struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
-+      struct cvmx_npei_dbg_data_cn56xx {
-+              uint64_t reserved_29_63:35;
-+              uint64_t qlm2_rev_lanes:1;
-+              uint64_t qlm0_rev_lanes:1;
-+              uint64_t qlm3_spd:2;
-+              uint64_t qlm1_spd:2;
-+              uint64_t c_mul:5;
-+              uint64_t dsel_ext:1;
-+              uint64_t data:17;
-+      } cn56xx;
-+      struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
-+};
-+
-+union cvmx_npei_dbg_select {
-+      uint64_t u64;
-+      struct cvmx_npei_dbg_select_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t dbg_sel:16;
-+      } s;
-+      struct cvmx_npei_dbg_select_s cn52xx;
-+      struct cvmx_npei_dbg_select_s cn52xxp1;
-+      struct cvmx_npei_dbg_select_s cn56xx;
-+      struct cvmx_npei_dbg_select_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dmax_counts {
-+      uint64_t u64;
-+      struct cvmx_npei_dmax_counts_s {
-+              uint64_t reserved_39_63:25;
-+              uint64_t fcnt:7;
-+              uint64_t dbell:32;
-+      } s;
-+      struct cvmx_npei_dmax_counts_s cn52xx;
-+      struct cvmx_npei_dmax_counts_s cn52xxp1;
-+      struct cvmx_npei_dmax_counts_s cn56xx;
-+      struct cvmx_npei_dmax_counts_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dmax_dbell {
-+      uint32_t u32;
-+      struct cvmx_npei_dmax_dbell_s {
-+              uint32_t reserved_16_31:16;
-+              uint32_t dbell:16;
-+      } s;
-+      struct cvmx_npei_dmax_dbell_s cn52xx;
-+      struct cvmx_npei_dmax_dbell_s cn52xxp1;
-+      struct cvmx_npei_dmax_dbell_s cn56xx;
-+      struct cvmx_npei_dmax_dbell_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dmax_ibuff_saddr {
-+      uint64_t u64;
-+      struct cvmx_npei_dmax_ibuff_saddr_s {
-+              uint64_t reserved_37_63:27;
-+              uint64_t idle:1;
-+              uint64_t saddr:29;
-+              uint64_t reserved_0_6:7;
-+      } s;
-+      struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
-+              uint64_t reserved_36_63:28;
-+              uint64_t saddr:29;
-+              uint64_t reserved_0_6:7;
-+      } cn52xx;
-+      struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
-+      struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
-+      struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
-+};
-+
-+union cvmx_npei_dmax_naddr {
-+      uint64_t u64;
-+      struct cvmx_npei_dmax_naddr_s {
-+              uint64_t reserved_36_63:28;
-+              uint64_t addr:36;
-+      } s;
-+      struct cvmx_npei_dmax_naddr_s cn52xx;
-+      struct cvmx_npei_dmax_naddr_s cn52xxp1;
-+      struct cvmx_npei_dmax_naddr_s cn56xx;
-+      struct cvmx_npei_dmax_naddr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dma0_int_level {
-+      uint64_t u64;
-+      struct cvmx_npei_dma0_int_level_s {
-+              uint64_t time:32;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_dma0_int_level_s cn52xx;
-+      struct cvmx_npei_dma0_int_level_s cn52xxp1;
-+      struct cvmx_npei_dma0_int_level_s cn56xx;
-+      struct cvmx_npei_dma0_int_level_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dma1_int_level {
-+      uint64_t u64;
-+      struct cvmx_npei_dma1_int_level_s {
-+              uint64_t time:32;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_dma1_int_level_s cn52xx;
-+      struct cvmx_npei_dma1_int_level_s cn52xxp1;
-+      struct cvmx_npei_dma1_int_level_s cn56xx;
-+      struct cvmx_npei_dma1_int_level_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dma_cnts {
-+      uint64_t u64;
-+      struct cvmx_npei_dma_cnts_s {
-+              uint64_t dma1:32;
-+              uint64_t dma0:32;
-+      } s;
-+      struct cvmx_npei_dma_cnts_s cn52xx;
-+      struct cvmx_npei_dma_cnts_s cn52xxp1;
-+      struct cvmx_npei_dma_cnts_s cn56xx;
-+      struct cvmx_npei_dma_cnts_s cn56xxp1;
-+};
-+
-+union cvmx_npei_dma_control {
-+      uint64_t u64;
-+      struct cvmx_npei_dma_control_s {
-+              uint64_t reserved_39_63:25;
-+              uint64_t dma4_enb:1;
-+              uint64_t dma3_enb:1;
-+              uint64_t dma2_enb:1;
-+              uint64_t dma1_enb:1;
-+              uint64_t dma0_enb:1;
-+              uint64_t b0_lend:1;
-+              uint64_t dwb_denb:1;
-+              uint64_t dwb_ichk:9;
-+              uint64_t fpa_que:3;
-+              uint64_t o_add1:1;
-+              uint64_t o_ro:1;
-+              uint64_t o_ns:1;
-+              uint64_t o_es:2;
-+              uint64_t o_mode:1;
-+              uint64_t csize:14;
-+      } s;
-+      struct cvmx_npei_dma_control_s cn52xx;
-+      struct cvmx_npei_dma_control_cn52xxp1 {
-+              uint64_t reserved_38_63:26;
-+              uint64_t dma3_enb:1;
-+              uint64_t dma2_enb:1;
-+              uint64_t dma1_enb:1;
-+              uint64_t dma0_enb:1;
-+              uint64_t b0_lend:1;
-+              uint64_t dwb_denb:1;
-+              uint64_t dwb_ichk:9;
-+              uint64_t fpa_que:3;
-+              uint64_t o_add1:1;
-+              uint64_t o_ro:1;
-+              uint64_t o_ns:1;
-+              uint64_t o_es:2;
-+              uint64_t o_mode:1;
-+              uint64_t csize:14;
-+      } cn52xxp1;
-+      struct cvmx_npei_dma_control_s cn56xx;
-+      struct cvmx_npei_dma_control_s cn56xxp1;
-+};
-+
-+union cvmx_npei_int_a_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_int_a_enb_s {
-+              uint64_t reserved_10_63:54;
-+              uint64_t pout_err:1;
-+              uint64_t pin_bp:1;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } s;
-+      struct cvmx_npei_int_a_enb_cn52xx {
-+              uint64_t reserved_8_63:56;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } cn52xx;
-+      struct cvmx_npei_int_a_enb_cn52xxp1 {
-+              uint64_t reserved_2_63:62;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_a_enb_s cn56xx;
-+};
-+
-+union cvmx_npei_int_a_enb2 {
-+      uint64_t u64;
-+      struct cvmx_npei_int_a_enb2_s {
-+              uint64_t reserved_10_63:54;
-+              uint64_t pout_err:1;
-+              uint64_t pin_bp:1;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } s;
-+      struct cvmx_npei_int_a_enb2_cn52xx {
-+              uint64_t reserved_8_63:56;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t reserved_0_1:2;
-+      } cn52xx;
-+      struct cvmx_npei_int_a_enb2_cn52xxp1 {
-+              uint64_t reserved_2_63:62;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_a_enb2_s cn56xx;
-+};
-+
-+union cvmx_npei_int_a_sum {
-+      uint64_t u64;
-+      struct cvmx_npei_int_a_sum_s {
-+              uint64_t reserved_10_63:54;
-+              uint64_t pout_err:1;
-+              uint64_t pin_bp:1;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } s;
-+      struct cvmx_npei_int_a_sum_cn52xx {
-+              uint64_t reserved_8_63:56;
-+              uint64_t p1_rdlk:1;
-+              uint64_t p0_rdlk:1;
-+              uint64_t pgl_err:1;
-+              uint64_t pdi_err:1;
-+              uint64_t pop_err:1;
-+              uint64_t pins_err:1;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } cn52xx;
-+      struct cvmx_npei_int_a_sum_cn52xxp1 {
-+              uint64_t reserved_2_63:62;
-+              uint64_t dma1_cpl:1;
-+              uint64_t dma0_cpl:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_a_sum_s cn56xx;
-+};
-+
-+union cvmx_npei_int_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_int_enb_s {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_62_62:1;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npei_int_enb_s cn52xx;
-+      struct cvmx_npei_int_enb_cn52xxp1 {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_62_62:1;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_enb_s cn56xx;
-+      struct cvmx_npei_int_enb_cn56xxp1 {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_61_62:2;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t reserved_29_29:1;
-+              uint64_t c1_se:1;
-+              uint64_t reserved_27_27:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t reserved_22_22:1;
-+              uint64_t c0_se:1;
-+              uint64_t reserved_20_20:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn56xxp1;
-+};
-+
-+union cvmx_npei_int_enb2 {
-+      uint64_t u64;
-+      struct cvmx_npei_int_enb2_s {
-+              uint64_t reserved_62_63:2;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npei_int_enb2_s cn52xx;
-+      struct cvmx_npei_int_enb2_cn52xxp1 {
-+              uint64_t reserved_62_63:2;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_enb2_s cn56xx;
-+      struct cvmx_npei_int_enb2_cn56xxp1 {
-+              uint64_t reserved_61_63:3;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t reserved_29_29:1;
-+              uint64_t c1_se:1;
-+              uint64_t reserved_27_27:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t reserved_22_22:1;
-+              uint64_t c0_se:1;
-+              uint64_t reserved_20_20:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn56xxp1;
-+};
-+
-+union cvmx_npei_int_info {
-+      uint64_t u64;
-+      struct cvmx_npei_int_info_s {
-+              uint64_t reserved_12_63:52;
-+              uint64_t pidbof:6;
-+              uint64_t psldbof:6;
-+      } s;
-+      struct cvmx_npei_int_info_s cn52xx;
-+      struct cvmx_npei_int_info_s cn56xx;
-+      struct cvmx_npei_int_info_s cn56xxp1;
-+};
-+
-+union cvmx_npei_int_sum {
-+      uint64_t u64;
-+      struct cvmx_npei_int_sum_s {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_62_62:1;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npei_int_sum_s cn52xx;
-+      struct cvmx_npei_int_sum_cn52xxp1 {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_62_62:1;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t reserved_15_18:4;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn52xxp1;
-+      struct cvmx_npei_int_sum_s cn56xx;
-+      struct cvmx_npei_int_sum_cn56xxp1 {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_61_62:2;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t reserved_29_29:1;
-+              uint64_t c1_se:1;
-+              uint64_t reserved_27_27:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t reserved_22_22:1;
-+              uint64_t c0_se:1;
-+              uint64_t reserved_20_20:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t ptime:1;
-+              uint64_t pcnt:1;
-+              uint64_t pidbof:1;
-+              uint64_t psldbof:1;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t dma4dbo:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn56xxp1;
-+};
-+
-+union cvmx_npei_int_sum2 {
-+      uint64_t u64;
-+      struct cvmx_npei_int_sum2_s {
-+              uint64_t mio_inta:1;
-+              uint64_t reserved_62_62:1;
-+              uint64_t int_a:1;
-+              uint64_t c1_ldwn:1;
-+              uint64_t c0_ldwn:1;
-+              uint64_t c1_exc:1;
-+              uint64_t c0_exc:1;
-+              uint64_t c1_up_wf:1;
-+              uint64_t c0_up_wf:1;
-+              uint64_t c1_un_wf:1;
-+              uint64_t c0_un_wf:1;
-+              uint64_t c1_un_bx:1;
-+              uint64_t c1_un_wi:1;
-+              uint64_t c1_un_b2:1;
-+              uint64_t c1_un_b1:1;
-+              uint64_t c1_un_b0:1;
-+              uint64_t c1_up_bx:1;
-+              uint64_t c1_up_wi:1;
-+              uint64_t c1_up_b2:1;
-+              uint64_t c1_up_b1:1;
-+              uint64_t c1_up_b0:1;
-+              uint64_t c0_un_bx:1;
-+              uint64_t c0_un_wi:1;
-+              uint64_t c0_un_b2:1;
-+              uint64_t c0_un_b1:1;
-+              uint64_t c0_un_b0:1;
-+              uint64_t c0_up_bx:1;
-+              uint64_t c0_up_wi:1;
-+              uint64_t c0_up_b2:1;
-+              uint64_t c0_up_b1:1;
-+              uint64_t c0_up_b0:1;
-+              uint64_t c1_hpint:1;
-+              uint64_t c1_pmei:1;
-+              uint64_t c1_wake:1;
-+              uint64_t crs1_dr:1;
-+              uint64_t c1_se:1;
-+              uint64_t crs1_er:1;
-+              uint64_t c1_aeri:1;
-+              uint64_t c0_hpint:1;
-+              uint64_t c0_pmei:1;
-+              uint64_t c0_wake:1;
-+              uint64_t crs0_dr:1;
-+              uint64_t c0_se:1;
-+              uint64_t crs0_er:1;
-+              uint64_t c0_aeri:1;
-+              uint64_t reserved_15_18:4;
-+              uint64_t dtime1:1;
-+              uint64_t dtime0:1;
-+              uint64_t dcnt1:1;
-+              uint64_t dcnt0:1;
-+              uint64_t dma1fi:1;
-+              uint64_t dma0fi:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t dma3dbo:1;
-+              uint64_t dma2dbo:1;
-+              uint64_t dma1dbo:1;
-+              uint64_t dma0dbo:1;
-+              uint64_t iob2big:1;
-+              uint64_t bar0_to:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npei_int_sum2_s cn52xx;
-+      struct cvmx_npei_int_sum2_s cn52xxp1;
-+      struct cvmx_npei_int_sum2_s cn56xx;
-+};
-+
-+union cvmx_npei_last_win_rdata0 {
-+      uint64_t u64;
-+      struct cvmx_npei_last_win_rdata0_s {
-+              uint64_t data:64;
-+      } s;
-+      struct cvmx_npei_last_win_rdata0_s cn52xx;
-+      struct cvmx_npei_last_win_rdata0_s cn52xxp1;
-+      struct cvmx_npei_last_win_rdata0_s cn56xx;
-+      struct cvmx_npei_last_win_rdata0_s cn56xxp1;
-+};
-+
-+union cvmx_npei_last_win_rdata1 {
-+      uint64_t u64;
-+      struct cvmx_npei_last_win_rdata1_s {
-+              uint64_t data:64;
-+      } s;
-+      struct cvmx_npei_last_win_rdata1_s cn52xx;
-+      struct cvmx_npei_last_win_rdata1_s cn52xxp1;
-+      struct cvmx_npei_last_win_rdata1_s cn56xx;
-+      struct cvmx_npei_last_win_rdata1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_mem_access_ctl {
-+      uint64_t u64;
-+      struct cvmx_npei_mem_access_ctl_s {
-+              uint64_t reserved_14_63:50;
-+              uint64_t max_word:4;
-+              uint64_t timer:10;
-+      } s;
-+      struct cvmx_npei_mem_access_ctl_s cn52xx;
-+      struct cvmx_npei_mem_access_ctl_s cn52xxp1;
-+      struct cvmx_npei_mem_access_ctl_s cn56xx;
-+      struct cvmx_npei_mem_access_ctl_s cn56xxp1;
-+};
-+
-+union cvmx_npei_mem_access_subidx {
-+      uint64_t u64;
-+      struct cvmx_npei_mem_access_subidx_s {
-+              uint64_t reserved_42_63:22;
-+              uint64_t zero:1;
-+              uint64_t port:2;
-+              uint64_t nmerge:1;
-+              uint64_t esr:2;
-+              uint64_t esw:2;
-+              uint64_t nsr:1;
-+              uint64_t nsw:1;
-+              uint64_t ror:1;
-+              uint64_t row:1;
-+              uint64_t ba:30;
-+      } s;
-+      struct cvmx_npei_mem_access_subidx_s cn52xx;
-+      struct cvmx_npei_mem_access_subidx_s cn52xxp1;
-+      struct cvmx_npei_mem_access_subidx_s cn56xx;
-+      struct cvmx_npei_mem_access_subidx_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_enb0 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_enb0_s {
-+              uint64_t enb:64;
-+      } s;
-+      struct cvmx_npei_msi_enb0_s cn52xx;
-+      struct cvmx_npei_msi_enb0_s cn52xxp1;
-+      struct cvmx_npei_msi_enb0_s cn56xx;
-+      struct cvmx_npei_msi_enb0_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_enb1 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_enb1_s {
-+              uint64_t enb:64;
-+      } s;
-+      struct cvmx_npei_msi_enb1_s cn52xx;
-+      struct cvmx_npei_msi_enb1_s cn52xxp1;
-+      struct cvmx_npei_msi_enb1_s cn56xx;
-+      struct cvmx_npei_msi_enb1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_enb2 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_enb2_s {
-+              uint64_t enb:64;
-+      } s;
-+      struct cvmx_npei_msi_enb2_s cn52xx;
-+      struct cvmx_npei_msi_enb2_s cn52xxp1;
-+      struct cvmx_npei_msi_enb2_s cn56xx;
-+      struct cvmx_npei_msi_enb2_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_enb3 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_enb3_s {
-+              uint64_t enb:64;
-+      } s;
-+      struct cvmx_npei_msi_enb3_s cn52xx;
-+      struct cvmx_npei_msi_enb3_s cn52xxp1;
-+      struct cvmx_npei_msi_enb3_s cn56xx;
-+      struct cvmx_npei_msi_enb3_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_rcv0 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_rcv0_s {
-+              uint64_t intr:64;
-+      } s;
-+      struct cvmx_npei_msi_rcv0_s cn52xx;
-+      struct cvmx_npei_msi_rcv0_s cn52xxp1;
-+      struct cvmx_npei_msi_rcv0_s cn56xx;
-+      struct cvmx_npei_msi_rcv0_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_rcv1 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_rcv1_s {
-+              uint64_t intr:64;
-+      } s;
-+      struct cvmx_npei_msi_rcv1_s cn52xx;
-+      struct cvmx_npei_msi_rcv1_s cn52xxp1;
-+      struct cvmx_npei_msi_rcv1_s cn56xx;
-+      struct cvmx_npei_msi_rcv1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_rcv2 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_rcv2_s {
-+              uint64_t intr:64;
-+      } s;
-+      struct cvmx_npei_msi_rcv2_s cn52xx;
-+      struct cvmx_npei_msi_rcv2_s cn52xxp1;
-+      struct cvmx_npei_msi_rcv2_s cn56xx;
-+      struct cvmx_npei_msi_rcv2_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_rcv3 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_rcv3_s {
-+              uint64_t intr:64;
-+      } s;
-+      struct cvmx_npei_msi_rcv3_s cn52xx;
-+      struct cvmx_npei_msi_rcv3_s cn52xxp1;
-+      struct cvmx_npei_msi_rcv3_s cn56xx;
-+      struct cvmx_npei_msi_rcv3_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_rd_map {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_rd_map_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t rd_int:8;
-+              uint64_t msi_int:8;
-+      } s;
-+      struct cvmx_npei_msi_rd_map_s cn52xx;
-+      struct cvmx_npei_msi_rd_map_s cn52xxp1;
-+      struct cvmx_npei_msi_rd_map_s cn56xx;
-+      struct cvmx_npei_msi_rd_map_s cn56xxp1;
-+};
-+
-+union cvmx_npei_msi_w1c_enb0 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1c_enb0_s {
-+              uint64_t clr:64;
-+      } s;
-+      struct cvmx_npei_msi_w1c_enb0_s cn52xx;
-+      struct cvmx_npei_msi_w1c_enb0_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1c_enb1 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1c_enb1_s {
-+              uint64_t clr:64;
-+      } s;
-+      struct cvmx_npei_msi_w1c_enb1_s cn52xx;
-+      struct cvmx_npei_msi_w1c_enb1_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1c_enb2 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1c_enb2_s {
-+              uint64_t clr:64;
-+      } s;
-+      struct cvmx_npei_msi_w1c_enb2_s cn52xx;
-+      struct cvmx_npei_msi_w1c_enb2_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1c_enb3 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1c_enb3_s {
-+              uint64_t clr:64;
-+      } s;
-+      struct cvmx_npei_msi_w1c_enb3_s cn52xx;
-+      struct cvmx_npei_msi_w1c_enb3_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1s_enb0 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1s_enb0_s {
-+              uint64_t set:64;
-+      } s;
-+      struct cvmx_npei_msi_w1s_enb0_s cn52xx;
-+      struct cvmx_npei_msi_w1s_enb0_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1s_enb1 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1s_enb1_s {
-+              uint64_t set:64;
-+      } s;
-+      struct cvmx_npei_msi_w1s_enb1_s cn52xx;
-+      struct cvmx_npei_msi_w1s_enb1_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1s_enb2 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1s_enb2_s {
-+              uint64_t set:64;
-+      } s;
-+      struct cvmx_npei_msi_w1s_enb2_s cn52xx;
-+      struct cvmx_npei_msi_w1s_enb2_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_w1s_enb3 {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_w1s_enb3_s {
-+              uint64_t set:64;
-+      } s;
-+      struct cvmx_npei_msi_w1s_enb3_s cn52xx;
-+      struct cvmx_npei_msi_w1s_enb3_s cn56xx;
-+};
-+
-+union cvmx_npei_msi_wr_map {
-+      uint64_t u64;
-+      struct cvmx_npei_msi_wr_map_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t ciu_int:8;
-+              uint64_t msi_int:8;
-+      } s;
-+      struct cvmx_npei_msi_wr_map_s cn52xx;
-+      struct cvmx_npei_msi_wr_map_s cn52xxp1;
-+      struct cvmx_npei_msi_wr_map_s cn56xx;
-+      struct cvmx_npei_msi_wr_map_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pcie_credit_cnt {
-+      uint64_t u64;
-+      struct cvmx_npei_pcie_credit_cnt_s {
-+              uint64_t reserved_48_63:16;
-+              uint64_t p1_ccnt:8;
-+              uint64_t p1_ncnt:8;
-+              uint64_t p1_pcnt:8;
-+              uint64_t p0_ccnt:8;
-+              uint64_t p0_ncnt:8;
-+              uint64_t p0_pcnt:8;
-+      } s;
-+      struct cvmx_npei_pcie_credit_cnt_s cn52xx;
-+      struct cvmx_npei_pcie_credit_cnt_s cn56xx;
-+};
-+
-+union cvmx_npei_pcie_msi_rcv {
-+      uint64_t u64;
-+      struct cvmx_npei_pcie_msi_rcv_s {
-+              uint64_t reserved_8_63:56;
-+              uint64_t intr:8;
-+      } s;
-+      struct cvmx_npei_pcie_msi_rcv_s cn52xx;
-+      struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
-+      struct cvmx_npei_pcie_msi_rcv_s cn56xx;
-+      struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pcie_msi_rcv_b1 {
-+      uint64_t u64;
-+      struct cvmx_npei_pcie_msi_rcv_b1_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t intr:8;
-+              uint64_t reserved_0_7:8;
-+      } s;
-+      struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
-+      struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
-+      struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
-+      struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pcie_msi_rcv_b2 {
-+      uint64_t u64;
-+      struct cvmx_npei_pcie_msi_rcv_b2_s {
-+              uint64_t reserved_24_63:40;
-+              uint64_t intr:8;
-+              uint64_t reserved_0_15:16;
-+      } s;
-+      struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
-+      struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
-+      struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
-+      struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pcie_msi_rcv_b3 {
-+      uint64_t u64;
-+      struct cvmx_npei_pcie_msi_rcv_b3_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t intr:8;
-+              uint64_t reserved_0_23:24;
-+      } s;
-+      struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
-+      struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
-+      struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
-+      struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_cnts {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_cnts_s {
-+              uint64_t reserved_54_63:10;
-+              uint64_t timer:22;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_pktx_cnts_s cn52xx;
-+      struct cvmx_npei_pktx_cnts_s cn56xx;
-+      struct cvmx_npei_pktx_cnts_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_in_bp {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_in_bp_s {
-+              uint64_t wmark:32;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_pktx_in_bp_s cn52xx;
-+      struct cvmx_npei_pktx_in_bp_s cn56xx;
-+      struct cvmx_npei_pktx_in_bp_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_instr_baddr {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_instr_baddr_s {
-+              uint64_t addr:61;
-+              uint64_t reserved_0_2:3;
-+      } s;
-+      struct cvmx_npei_pktx_instr_baddr_s cn52xx;
-+      struct cvmx_npei_pktx_instr_baddr_s cn56xx;
-+      struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_instr_baoff_dbell {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_instr_baoff_dbell_s {
-+              uint64_t aoff:32;
-+              uint64_t dbell:32;
-+      } s;
-+      struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
-+      struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
-+      struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_instr_fifo_rsize {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_instr_fifo_rsize_s {
-+              uint64_t max:9;
-+              uint64_t rrp:9;
-+              uint64_t wrp:9;
-+              uint64_t fcnt:5;
-+              uint64_t rsize:32;
-+      } s;
-+      struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
-+      struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
-+      struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_instr_header {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_instr_header_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t pbp:1;
-+              uint64_t rsv_f:5;
-+              uint64_t rparmode:2;
-+              uint64_t rsv_e:1;
-+              uint64_t rskp_len:7;
-+              uint64_t rsv_d:6;
-+              uint64_t use_ihdr:1;
-+              uint64_t rsv_c:5;
-+              uint64_t par_mode:2;
-+              uint64_t rsv_b:1;
-+              uint64_t skp_len:7;
-+              uint64_t rsv_a:6;
-+      } s;
-+      struct cvmx_npei_pktx_instr_header_s cn52xx;
-+      struct cvmx_npei_pktx_instr_header_s cn56xx;
-+      struct cvmx_npei_pktx_instr_header_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_slist_baddr {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_slist_baddr_s {
-+              uint64_t addr:60;
-+              uint64_t reserved_0_3:4;
-+      } s;
-+      struct cvmx_npei_pktx_slist_baddr_s cn52xx;
-+      struct cvmx_npei_pktx_slist_baddr_s cn56xx;
-+      struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_slist_baoff_dbell {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_slist_baoff_dbell_s {
-+              uint64_t aoff:32;
-+              uint64_t dbell:32;
-+      } s;
-+      struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
-+      struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
-+      struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pktx_slist_fifo_rsize {
-+      uint64_t u64;
-+      struct cvmx_npei_pktx_slist_fifo_rsize_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t rsize:32;
-+      } s;
-+      struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
-+      struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
-+      struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_cnt_int {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_cnt_int_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t port:32;
-+      } s;
-+      struct cvmx_npei_pkt_cnt_int_s cn52xx;
-+      struct cvmx_npei_pkt_cnt_int_s cn56xx;
-+      struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_cnt_int_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_cnt_int_enb_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t port:32;
-+      } s;
-+      struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
-+      struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
-+      struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_data_out_es {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_data_out_es_s {
-+              uint64_t es:64;
-+      } s;
-+      struct cvmx_npei_pkt_data_out_es_s cn52xx;
-+      struct cvmx_npei_pkt_data_out_es_s cn56xx;
-+      struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_data_out_ns {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_data_out_ns_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t nsr:32;
-+      } s;
-+      struct cvmx_npei_pkt_data_out_ns_s cn52xx;
-+      struct cvmx_npei_pkt_data_out_ns_s cn56xx;
-+      struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_data_out_ror {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_data_out_ror_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t ror:32;
-+      } s;
-+      struct cvmx_npei_pkt_data_out_ror_s cn52xx;
-+      struct cvmx_npei_pkt_data_out_ror_s cn56xx;
-+      struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_dpaddr {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_dpaddr_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t dptr:32;
-+      } s;
-+      struct cvmx_npei_pkt_dpaddr_s cn52xx;
-+      struct cvmx_npei_pkt_dpaddr_s cn56xx;
-+      struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_in_bp {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_in_bp_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t bp:32;
-+      } s;
-+      struct cvmx_npei_pkt_in_bp_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_in_donex_cnts {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_in_donex_cnts_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
-+      struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
-+      struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_in_instr_counts {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_in_instr_counts_s {
-+              uint64_t wr_cnt:32;
-+              uint64_t rd_cnt:32;
-+      } s;
-+      struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
-+      struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_in_pcie_port {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_in_pcie_port_s {
-+              uint64_t pp:64;
-+      } s;
-+      struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
-+      struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_input_control {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_input_control_s {
-+              uint64_t reserved_23_63:41;
-+              uint64_t pkt_rr:1;
-+              uint64_t pbp_dhi:13;
-+              uint64_t d_nsr:1;
-+              uint64_t d_esr:2;
-+              uint64_t d_ror:1;
-+              uint64_t use_csr:1;
-+              uint64_t nsr:1;
-+              uint64_t esr:2;
-+              uint64_t ror:1;
-+      } s;
-+      struct cvmx_npei_pkt_input_control_s cn52xx;
-+      struct cvmx_npei_pkt_input_control_s cn56xx;
-+      struct cvmx_npei_pkt_input_control_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_instr_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_instr_enb_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t enb:32;
-+      } s;
-+      struct cvmx_npei_pkt_instr_enb_s cn52xx;
-+      struct cvmx_npei_pkt_instr_enb_s cn56xx;
-+      struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_instr_rd_size {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_instr_rd_size_s {
-+              uint64_t rdsize:64;
-+      } s;
-+      struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
-+      struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_instr_size {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_instr_size_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t is_64b:32;
-+      } s;
-+      struct cvmx_npei_pkt_instr_size_s cn52xx;
-+      struct cvmx_npei_pkt_instr_size_s cn56xx;
-+      struct cvmx_npei_pkt_instr_size_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_int_levels {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_int_levels_s {
-+              uint64_t reserved_54_63:10;
-+              uint64_t time:22;
-+              uint64_t cnt:32;
-+      } s;
-+      struct cvmx_npei_pkt_int_levels_s cn52xx;
-+      struct cvmx_npei_pkt_int_levels_s cn56xx;
-+      struct cvmx_npei_pkt_int_levels_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_iptr {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_iptr_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t iptr:32;
-+      } s;
-+      struct cvmx_npei_pkt_iptr_s cn52xx;
-+      struct cvmx_npei_pkt_iptr_s cn56xx;
-+      struct cvmx_npei_pkt_iptr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_out_bmode {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_out_bmode_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t bmode:32;
-+      } s;
-+      struct cvmx_npei_pkt_out_bmode_s cn52xx;
-+      struct cvmx_npei_pkt_out_bmode_s cn56xx;
-+      struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_out_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_out_enb_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t enb:32;
-+      } s;
-+      struct cvmx_npei_pkt_out_enb_s cn52xx;
-+      struct cvmx_npei_pkt_out_enb_s cn56xx;
-+      struct cvmx_npei_pkt_out_enb_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_output_wmark {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_output_wmark_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t wmark:32;
-+      } s;
-+      struct cvmx_npei_pkt_output_wmark_s cn52xx;
-+      struct cvmx_npei_pkt_output_wmark_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_pcie_port {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_pcie_port_s {
-+              uint64_t pp:64;
-+      } s;
-+      struct cvmx_npei_pkt_pcie_port_s cn52xx;
-+      struct cvmx_npei_pkt_pcie_port_s cn56xx;
-+      struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_port_in_rst {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_port_in_rst_s {
-+              uint64_t in_rst:32;
-+              uint64_t out_rst:32;
-+      } s;
-+      struct cvmx_npei_pkt_port_in_rst_s cn52xx;
-+      struct cvmx_npei_pkt_port_in_rst_s cn56xx;
-+};
-+
-+union cvmx_npei_pkt_slist_es {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_slist_es_s {
-+              uint64_t es:64;
-+      } s;
-+      struct cvmx_npei_pkt_slist_es_s cn52xx;
-+      struct cvmx_npei_pkt_slist_es_s cn56xx;
-+      struct cvmx_npei_pkt_slist_es_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_slist_id_size {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_slist_id_size_s {
-+              uint64_t reserved_23_63:41;
-+              uint64_t isize:7;
-+              uint64_t bsize:16;
-+      } s;
-+      struct cvmx_npei_pkt_slist_id_size_s cn52xx;
-+      struct cvmx_npei_pkt_slist_id_size_s cn56xx;
-+      struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_slist_ns {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_slist_ns_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t nsr:32;
-+      } s;
-+      struct cvmx_npei_pkt_slist_ns_s cn52xx;
-+      struct cvmx_npei_pkt_slist_ns_s cn56xx;
-+      struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_slist_ror {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_slist_ror_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t ror:32;
-+      } s;
-+      struct cvmx_npei_pkt_slist_ror_s cn52xx;
-+      struct cvmx_npei_pkt_slist_ror_s cn56xx;
-+      struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_time_int {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_time_int_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t port:32;
-+      } s;
-+      struct cvmx_npei_pkt_time_int_s cn52xx;
-+      struct cvmx_npei_pkt_time_int_s cn56xx;
-+      struct cvmx_npei_pkt_time_int_s cn56xxp1;
-+};
-+
-+union cvmx_npei_pkt_time_int_enb {
-+      uint64_t u64;
-+      struct cvmx_npei_pkt_time_int_enb_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t port:32;
-+      } s;
-+      struct cvmx_npei_pkt_time_int_enb_s cn52xx;
-+      struct cvmx_npei_pkt_time_int_enb_s cn56xx;
-+      struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
-+};
-+
-+union cvmx_npei_rsl_int_blocks {
-+      uint64_t u64;
-+      struct cvmx_npei_rsl_int_blocks_s {
-+              uint64_t reserved_31_63:33;
-+              uint64_t iob:1;
-+              uint64_t lmc1:1;
-+              uint64_t agl:1;
-+              uint64_t reserved_24_27:4;
-+              uint64_t asxpcs1:1;
-+              uint64_t asxpcs0:1;
-+              uint64_t reserved_21_21:1;
-+              uint64_t pip:1;
-+              uint64_t reserved_18_19:2;
-+              uint64_t lmc0:1;
-+              uint64_t l2c:1;
-+              uint64_t usb1:1;
-+              uint64_t rad:1;
-+              uint64_t usb:1;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t zip:1;
-+              uint64_t reserved_6_6:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npei:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } s;
-+      struct cvmx_npei_rsl_int_blocks_s cn52xx;
-+      struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
-+      struct cvmx_npei_rsl_int_blocks_cn56xx {
-+              uint64_t reserved_31_63:33;
-+              uint64_t iob:1;
-+              uint64_t lmc1:1;
-+              uint64_t agl:1;
-+              uint64_t reserved_24_27:4;
-+              uint64_t asxpcs1:1;
-+              uint64_t asxpcs0:1;
-+              uint64_t reserved_21_21:1;
-+              uint64_t pip:1;
-+              uint64_t reserved_18_19:2;
-+              uint64_t lmc0:1;
-+              uint64_t l2c:1;
-+              uint64_t reserved_15_15:1;
-+              uint64_t rad:1;
-+              uint64_t usb:1;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t zip:1;
-+              uint64_t reserved_6_6:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npei:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } cn56xx;
-+      struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
-+};
-+
-+union cvmx_npei_scratch_1 {
-+      uint64_t u64;
-+      struct cvmx_npei_scratch_1_s {
-+              uint64_t data:64;
-+      } s;
-+      struct cvmx_npei_scratch_1_s cn52xx;
-+      struct cvmx_npei_scratch_1_s cn52xxp1;
-+      struct cvmx_npei_scratch_1_s cn56xx;
-+      struct cvmx_npei_scratch_1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_state1 {
-+      uint64_t u64;
-+      struct cvmx_npei_state1_s {
-+              uint64_t cpl1:12;
-+              uint64_t cpl0:12;
-+              uint64_t arb:1;
-+              uint64_t csr:39;
-+      } s;
-+      struct cvmx_npei_state1_s cn52xx;
-+      struct cvmx_npei_state1_s cn52xxp1;
-+      struct cvmx_npei_state1_s cn56xx;
-+      struct cvmx_npei_state1_s cn56xxp1;
-+};
-+
-+union cvmx_npei_state2 {
-+      uint64_t u64;
-+      struct cvmx_npei_state2_s {
-+              uint64_t reserved_48_63:16;
-+              uint64_t npei:1;
-+              uint64_t rac:1;
-+              uint64_t csm1:15;
-+              uint64_t csm0:15;
-+              uint64_t nnp0:8;
-+              uint64_t nnd:8;
-+      } s;
-+      struct cvmx_npei_state2_s cn52xx;
-+      struct cvmx_npei_state2_s cn52xxp1;
-+      struct cvmx_npei_state2_s cn56xx;
-+      struct cvmx_npei_state2_s cn56xxp1;
-+};
-+
-+union cvmx_npei_state3 {
-+      uint64_t u64;
-+      struct cvmx_npei_state3_s {
-+              uint64_t reserved_56_63:8;
-+              uint64_t psm1:15;
-+              uint64_t psm0:15;
-+              uint64_t nsm1:13;
-+              uint64_t nsm0:13;
-+      } s;
-+      struct cvmx_npei_state3_s cn52xx;
-+      struct cvmx_npei_state3_s cn52xxp1;
-+      struct cvmx_npei_state3_s cn56xx;
-+      struct cvmx_npei_state3_s cn56xxp1;
-+};
-+
-+union cvmx_npei_win_rd_addr {
-+      uint64_t u64;
-+      struct cvmx_npei_win_rd_addr_s {
-+              uint64_t reserved_51_63:13;
-+              uint64_t ld_cmd:2;
-+              uint64_t iobit:1;
-+              uint64_t rd_addr:48;
-+      } s;
-+      struct cvmx_npei_win_rd_addr_s cn52xx;
-+      struct cvmx_npei_win_rd_addr_s cn52xxp1;
-+      struct cvmx_npei_win_rd_addr_s cn56xx;
-+      struct cvmx_npei_win_rd_addr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_win_rd_data {
-+      uint64_t u64;
-+      struct cvmx_npei_win_rd_data_s {
-+              uint64_t rd_data:64;
-+      } s;
-+      struct cvmx_npei_win_rd_data_s cn52xx;
-+      struct cvmx_npei_win_rd_data_s cn52xxp1;
-+      struct cvmx_npei_win_rd_data_s cn56xx;
-+      struct cvmx_npei_win_rd_data_s cn56xxp1;
-+};
-+
-+union cvmx_npei_win_wr_addr {
-+      uint64_t u64;
-+      struct cvmx_npei_win_wr_addr_s {
-+              uint64_t reserved_49_63:15;
-+              uint64_t iobit:1;
-+              uint64_t wr_addr:46;
-+              uint64_t reserved_0_1:2;
-+      } s;
-+      struct cvmx_npei_win_wr_addr_s cn52xx;
-+      struct cvmx_npei_win_wr_addr_s cn52xxp1;
-+      struct cvmx_npei_win_wr_addr_s cn56xx;
-+      struct cvmx_npei_win_wr_addr_s cn56xxp1;
-+};
-+
-+union cvmx_npei_win_wr_data {
-+      uint64_t u64;
-+      struct cvmx_npei_win_wr_data_s {
-+              uint64_t wr_data:64;
-+      } s;
-+      struct cvmx_npei_win_wr_data_s cn52xx;
-+      struct cvmx_npei_win_wr_data_s cn52xxp1;
-+      struct cvmx_npei_win_wr_data_s cn56xx;
-+      struct cvmx_npei_win_wr_data_s cn56xxp1;
-+};
-+
-+union cvmx_npei_win_wr_mask {
-+      uint64_t u64;
-+      struct cvmx_npei_win_wr_mask_s {
-+              uint64_t reserved_8_63:56;
-+              uint64_t wr_mask:8;
-+      } s;
-+      struct cvmx_npei_win_wr_mask_s cn52xx;
-+      struct cvmx_npei_win_wr_mask_s cn52xxp1;
-+      struct cvmx_npei_win_wr_mask_s cn56xx;
-+      struct cvmx_npei_win_wr_mask_s cn56xxp1;
-+};
-+
-+union cvmx_npei_window_ctl {
-+      uint64_t u64;
-+      struct cvmx_npei_window_ctl_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t time:32;
-+      } s;
-+      struct cvmx_npei_window_ctl_s cn52xx;
-+      struct cvmx_npei_window_ctl_s cn52xxp1;
-+      struct cvmx_npei_window_ctl_s cn56xx;
-+      struct cvmx_npei_window_ctl_s cn56xxp1;
-+};
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
-@@ -0,0 +1,1735 @@
-+/***********************license start***************
-+ * Author: Cavium Networks
-+ *
-+ * Contact: support@caviumnetworks.com
-+ * This file is part of the OCTEON SDK
-+ *
-+ * Copyright (c) 2003-2008 Cavium Networks
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ *
-+ * This file is distributed in the hope that it will be useful, but
-+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
-+ * NONINFRINGEMENT.  See the GNU General Public License for more
-+ * details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this file; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ * or visit http://www.gnu.org/licenses/.
-+ *
-+ * This file may also be available under a different license from Cavium.
-+ * Contact Cavium Networks for more information
-+ ***********************license end**************************************/
-+
-+#ifndef __CVMX_NPI_DEFS_H__
-+#define __CVMX_NPI_DEFS_H__
-+
-+#define CVMX_NPI_BASE_ADDR_INPUT0 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000070ull)
-+#define CVMX_NPI_BASE_ADDR_INPUT1 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000080ull)
-+#define CVMX_NPI_BASE_ADDR_INPUT2 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000090ull)
-+#define CVMX_NPI_BASE_ADDR_INPUT3 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
-+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
-+#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
-+#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
-+#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
-+#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
-+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_BIST_STATUS \
-+       CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
-+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
-+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
-+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
-+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
-+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_COMP_CTL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000218ull)
-+#define CVMX_NPI_CTL_STATUS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000010ull)
-+#define CVMX_NPI_DBG_SELECT \
-+       CVMX_ADD_IO_SEG(0x00011F0000000008ull)
-+#define CVMX_NPI_DMA_CONTROL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000128ull)
-+#define CVMX_NPI_DMA_HIGHP_COUNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000148ull)
-+#define CVMX_NPI_DMA_HIGHP_NADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000158ull)
-+#define CVMX_NPI_DMA_LOWP_COUNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000140ull)
-+#define CVMX_NPI_DMA_LOWP_NADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000150ull)
-+#define CVMX_NPI_HIGHP_DBELL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000120ull)
-+#define CVMX_NPI_HIGHP_IBUFF_SADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000110ull)
-+#define CVMX_NPI_INPUT_CONTROL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000138ull)
-+#define CVMX_NPI_INT_ENB \
-+       CVMX_ADD_IO_SEG(0x00011F0000000020ull)
-+#define CVMX_NPI_INT_SUM \
-+       CVMX_ADD_IO_SEG(0x00011F0000000018ull)
-+#define CVMX_NPI_LOWP_DBELL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000118ull)
-+#define CVMX_NPI_LOWP_IBUFF_SADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000108ull)
-+#define CVMX_NPI_MEM_ACCESS_SUBID3 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000028ull)
-+#define CVMX_NPI_MEM_ACCESS_SUBID4 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000030ull)
-+#define CVMX_NPI_MEM_ACCESS_SUBID5 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000038ull)
-+#define CVMX_NPI_MEM_ACCESS_SUBID6 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000040ull)
-+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
-+#define CVMX_NPI_MSI_RCV \
-+       (0x0000000000000190ull)
-+#define CVMX_NPI_NPI_MSI_RCV \
-+       CVMX_ADD_IO_SEG(0x00011F0000001190ull)
-+#define CVMX_NPI_NUM_DESC_OUTPUT0 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000050ull)
-+#define CVMX_NPI_NUM_DESC_OUTPUT1 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000058ull)
-+#define CVMX_NPI_NUM_DESC_OUTPUT2 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000060ull)
-+#define CVMX_NPI_NUM_DESC_OUTPUT3 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000068ull)
-+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_OUTPUT_CONTROL \
-+       CVMX_ADD_IO_SEG(0x00011F0000000100ull)
-+#define CVMX_NPI_P0_DBPAIR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000180ull)
-+#define CVMX_NPI_P0_INSTR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
-+#define CVMX_NPI_P0_INSTR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
-+#define CVMX_NPI_P0_PAIR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000160ull)
-+#define CVMX_NPI_P1_DBPAIR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000188ull)
-+#define CVMX_NPI_P1_INSTR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
-+#define CVMX_NPI_P1_INSTR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
-+#define CVMX_NPI_P1_PAIR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000168ull)
-+#define CVMX_NPI_P2_DBPAIR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000190ull)
-+#define CVMX_NPI_P2_INSTR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
-+#define CVMX_NPI_P2_INSTR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
-+#define CVMX_NPI_P2_PAIR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000170ull)
-+#define CVMX_NPI_P3_DBPAIR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000198ull)
-+#define CVMX_NPI_P3_INSTR_ADDR \
-+       CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
-+#define CVMX_NPI_P3_INSTR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
-+#define CVMX_NPI_P3_PAIR_CNTS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000178ull)
-+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
-+#define CVMX_NPI_PCI_BIST_REG \
-+       CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
-+#define CVMX_NPI_PCI_BURST_SIZE \
-+       CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
-+#define CVMX_NPI_PCI_CFG00 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001800ull)
-+#define CVMX_NPI_PCI_CFG01 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001804ull)
-+#define CVMX_NPI_PCI_CFG02 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001808ull)
-+#define CVMX_NPI_PCI_CFG03 \
-+       CVMX_ADD_IO_SEG(0x00011F000000180Cull)
-+#define CVMX_NPI_PCI_CFG04 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001810ull)
-+#define CVMX_NPI_PCI_CFG05 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001814ull)
-+#define CVMX_NPI_PCI_CFG06 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001818ull)
-+#define CVMX_NPI_PCI_CFG07 \
-+       CVMX_ADD_IO_SEG(0x00011F000000181Cull)
-+#define CVMX_NPI_PCI_CFG08 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001820ull)
-+#define CVMX_NPI_PCI_CFG09 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001824ull)
-+#define CVMX_NPI_PCI_CFG10 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001828ull)
-+#define CVMX_NPI_PCI_CFG11 \
-+       CVMX_ADD_IO_SEG(0x00011F000000182Cull)
-+#define CVMX_NPI_PCI_CFG12 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001830ull)
-+#define CVMX_NPI_PCI_CFG13 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001834ull)
-+#define CVMX_NPI_PCI_CFG15 \
-+       CVMX_ADD_IO_SEG(0x00011F000000183Cull)
-+#define CVMX_NPI_PCI_CFG16 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001840ull)
-+#define CVMX_NPI_PCI_CFG17 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001844ull)
-+#define CVMX_NPI_PCI_CFG18 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001848ull)
-+#define CVMX_NPI_PCI_CFG19 \
-+       CVMX_ADD_IO_SEG(0x00011F000000184Cull)
-+#define CVMX_NPI_PCI_CFG20 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001850ull)
-+#define CVMX_NPI_PCI_CFG21 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001854ull)
-+#define CVMX_NPI_PCI_CFG22 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001858ull)
-+#define CVMX_NPI_PCI_CFG56 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
-+#define CVMX_NPI_PCI_CFG57 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
-+#define CVMX_NPI_PCI_CFG58 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
-+#define CVMX_NPI_PCI_CFG59 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018ECull)
-+#define CVMX_NPI_PCI_CFG60 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
-+#define CVMX_NPI_PCI_CFG61 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
-+#define CVMX_NPI_PCI_CFG62 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
-+#define CVMX_NPI_PCI_CFG63 \
-+       CVMX_ADD_IO_SEG(0x00011F00000018FCull)
-+#define CVMX_NPI_PCI_CNT_REG \
-+       CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
-+#define CVMX_NPI_PCI_CTL_STATUS_2 \
-+       CVMX_ADD_IO_SEG(0x00011F000000118Cull)
-+#define CVMX_NPI_PCI_INT_ARB_CFG \
-+       CVMX_ADD_IO_SEG(0x00011F0000000130ull)
-+#define CVMX_NPI_PCI_INT_ENB2 \
-+       CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
-+#define CVMX_NPI_PCI_INT_SUM2 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001198ull)
-+#define CVMX_NPI_PCI_READ_CMD \
-+       CVMX_ADD_IO_SEG(0x00011F0000000048ull)
-+#define CVMX_NPI_PCI_READ_CMD_6 \
-+       CVMX_ADD_IO_SEG(0x00011F0000001180ull)
-+#define CVMX_NPI_PCI_READ_CMD_C \
-+       CVMX_ADD_IO_SEG(0x00011F0000001184ull)
-+#define CVMX_NPI_PCI_READ_CMD_E \
-+       CVMX_ADD_IO_SEG(0x00011F0000001188ull)
-+#define CVMX_NPI_PCI_SCM_REG \
-+       CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
-+#define CVMX_NPI_PCI_TSR_REG \
-+       CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
-+#define CVMX_NPI_PORT32_INSTR_HDR \
-+       CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
-+#define CVMX_NPI_PORT33_INSTR_HDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000200ull)
-+#define CVMX_NPI_PORT34_INSTR_HDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000208ull)
-+#define CVMX_NPI_PORT35_INSTR_HDR \
-+       CVMX_ADD_IO_SEG(0x00011F0000000210ull)
-+#define CVMX_NPI_PORT_BP_CONTROL \
-+       CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
-+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_PX_INSTR_ADDR(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_PX_INSTR_CNTS(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_PX_PAIR_CNTS(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
-+#define CVMX_NPI_RSL_INT_BLOCKS \
-+       CVMX_ADD_IO_SEG(0x00011F0000000000ull)
-+#define CVMX_NPI_SIZE_INPUT0 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000078ull)
-+#define CVMX_NPI_SIZE_INPUT1 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000088ull)
-+#define CVMX_NPI_SIZE_INPUT2 \
-+       CVMX_ADD_IO_SEG(0x00011F0000000098ull)
-+#define CVMX_NPI_SIZE_INPUT3 \
-+       CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
-+#define CVMX_NPI_SIZE_INPUTX(offset) \
-+       CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
-+#define CVMX_NPI_WIN_READ_TO \
-+       CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
-+
-+union cvmx_npi_base_addr_inputx {
-+      uint64_t u64;
-+      struct cvmx_npi_base_addr_inputx_s {
-+              uint64_t baddr:61;
-+              uint64_t reserved_0_2:3;
-+      } s;
-+      struct cvmx_npi_base_addr_inputx_s cn30xx;
-+      struct cvmx_npi_base_addr_inputx_s cn31xx;
-+      struct cvmx_npi_base_addr_inputx_s cn38xx;
-+      struct cvmx_npi_base_addr_inputx_s cn38xxp2;
-+      struct cvmx_npi_base_addr_inputx_s cn50xx;
-+      struct cvmx_npi_base_addr_inputx_s cn58xx;
-+      struct cvmx_npi_base_addr_inputx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_base_addr_outputx {
-+      uint64_t u64;
-+      struct cvmx_npi_base_addr_outputx_s {
-+              uint64_t baddr:61;
-+              uint64_t reserved_0_2:3;
-+      } s;
-+      struct cvmx_npi_base_addr_outputx_s cn30xx;
-+      struct cvmx_npi_base_addr_outputx_s cn31xx;
-+      struct cvmx_npi_base_addr_outputx_s cn38xx;
-+      struct cvmx_npi_base_addr_outputx_s cn38xxp2;
-+      struct cvmx_npi_base_addr_outputx_s cn50xx;
-+      struct cvmx_npi_base_addr_outputx_s cn58xx;
-+      struct cvmx_npi_base_addr_outputx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_bist_status {
-+      uint64_t u64;
-+      struct cvmx_npi_bist_status_s {
-+              uint64_t reserved_20_63:44;
-+              uint64_t csr_bs:1;
-+              uint64_t dif_bs:1;
-+              uint64_t rdp_bs:1;
-+              uint64_t pcnc_bs:1;
-+              uint64_t pcn_bs:1;
-+              uint64_t rdn_bs:1;
-+              uint64_t pcac_bs:1;
-+              uint64_t pcad_bs:1;
-+              uint64_t rdnl_bs:1;
-+              uint64_t pgf_bs:1;
-+              uint64_t pig_bs:1;
-+              uint64_t pof0_bs:1;
-+              uint64_t pof1_bs:1;
-+              uint64_t pof2_bs:1;
-+              uint64_t pof3_bs:1;
-+              uint64_t pos_bs:1;
-+              uint64_t nus_bs:1;
-+              uint64_t dob_bs:1;
-+              uint64_t pdf_bs:1;
-+              uint64_t dpi_bs:1;
-+      } s;
-+      struct cvmx_npi_bist_status_cn30xx {
-+              uint64_t reserved_20_63:44;
-+              uint64_t csr_bs:1;
-+              uint64_t dif_bs:1;
-+              uint64_t rdp_bs:1;
-+              uint64_t pcnc_bs:1;
-+              uint64_t pcn_bs:1;
-+              uint64_t rdn_bs:1;
-+              uint64_t pcac_bs:1;
-+              uint64_t pcad_bs:1;
-+              uint64_t rdnl_bs:1;
-+              uint64_t pgf_bs:1;
-+              uint64_t pig_bs:1;
-+              uint64_t pof0_bs:1;
-+              uint64_t reserved_5_7:3;
-+              uint64_t pos_bs:1;
-+              uint64_t nus_bs:1;
-+              uint64_t dob_bs:1;
-+              uint64_t pdf_bs:1;
-+              uint64_t dpi_bs:1;
-+      } cn30xx;
-+      struct cvmx_npi_bist_status_s cn31xx;
-+      struct cvmx_npi_bist_status_s cn38xx;
-+      struct cvmx_npi_bist_status_s cn38xxp2;
-+      struct cvmx_npi_bist_status_cn50xx {
-+              uint64_t reserved_20_63:44;
-+              uint64_t csr_bs:1;
-+              uint64_t dif_bs:1;
-+              uint64_t rdp_bs:1;
-+              uint64_t pcnc_bs:1;
-+              uint64_t pcn_bs:1;
-+              uint64_t rdn_bs:1;
-+              uint64_t pcac_bs:1;
-+              uint64_t pcad_bs:1;
-+              uint64_t rdnl_bs:1;
-+              uint64_t pgf_bs:1;
-+              uint64_t pig_bs:1;
-+              uint64_t pof0_bs:1;
-+              uint64_t pof1_bs:1;
-+              uint64_t reserved_5_6:2;
-+              uint64_t pos_bs:1;
-+              uint64_t nus_bs:1;
-+              uint64_t dob_bs:1;
-+              uint64_t pdf_bs:1;
-+              uint64_t dpi_bs:1;
-+      } cn50xx;
-+      struct cvmx_npi_bist_status_s cn58xx;
-+      struct cvmx_npi_bist_status_s cn58xxp1;
-+};
-+
-+union cvmx_npi_buff_size_outputx {
-+      uint64_t u64;
-+      struct cvmx_npi_buff_size_outputx_s {
-+              uint64_t reserved_23_63:41;
-+              uint64_t isize:7;
-+              uint64_t bsize:16;
-+      } s;
-+      struct cvmx_npi_buff_size_outputx_s cn30xx;
-+      struct cvmx_npi_buff_size_outputx_s cn31xx;
-+      struct cvmx_npi_buff_size_outputx_s cn38xx;
-+      struct cvmx_npi_buff_size_outputx_s cn38xxp2;
-+      struct cvmx_npi_buff_size_outputx_s cn50xx;
-+      struct cvmx_npi_buff_size_outputx_s cn58xx;
-+      struct cvmx_npi_buff_size_outputx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_comp_ctl {
-+      uint64_t u64;
-+      struct cvmx_npi_comp_ctl_s {
-+              uint64_t reserved_10_63:54;
-+              uint64_t pctl:5;
-+              uint64_t nctl:5;
-+      } s;
-+      struct cvmx_npi_comp_ctl_s cn50xx;
-+      struct cvmx_npi_comp_ctl_s cn58xx;
-+      struct cvmx_npi_comp_ctl_s cn58xxp1;
-+};
-+
-+union cvmx_npi_ctl_status {
-+      uint64_t u64;
-+      struct cvmx_npi_ctl_status_s {
-+              uint64_t reserved_63_63:1;
-+              uint64_t chip_rev:8;
-+              uint64_t dis_pniw:1;
-+              uint64_t out3_enb:1;
-+              uint64_t out2_enb:1;
-+              uint64_t out1_enb:1;
-+              uint64_t out0_enb:1;
-+              uint64_t ins3_enb:1;
-+              uint64_t ins2_enb:1;
-+              uint64_t ins1_enb:1;
-+              uint64_t ins0_enb:1;
-+              uint64_t ins3_64b:1;
-+              uint64_t ins2_64b:1;
-+              uint64_t ins1_64b:1;
-+              uint64_t ins0_64b:1;
-+              uint64_t pci_wdis:1;
-+              uint64_t wait_com:1;
-+              uint64_t reserved_37_39:3;
-+              uint64_t max_word:5;
-+              uint64_t reserved_10_31:22;
-+              uint64_t timer:10;
-+      } s;
-+      struct cvmx_npi_ctl_status_cn30xx {
-+              uint64_t reserved_63_63:1;
-+              uint64_t chip_rev:8;
-+              uint64_t dis_pniw:1;
-+              uint64_t reserved_51_53:3;
-+              uint64_t out0_enb:1;
-+              uint64_t reserved_47_49:3;
-+              uint64_t ins0_enb:1;
-+              uint64_t reserved_43_45:3;
-+              uint64_t ins0_64b:1;
-+              uint64_t pci_wdis:1;
-+              uint64_t wait_com:1;
-+              uint64_t reserved_37_39:3;
-+              uint64_t max_word:5;
-+              uint64_t reserved_10_31:22;
-+              uint64_t timer:10;
-+      } cn30xx;
-+      struct cvmx_npi_ctl_status_cn31xx {
-+              uint64_t reserved_63_63:1;
-+              uint64_t chip_rev:8;
-+              uint64_t dis_pniw:1;
-+              uint64_t reserved_52_53:2;
-+              uint64_t out1_enb:1;
-+              uint64_t out0_enb:1;
-+              uint64_t reserved_48_49:2;
-+              uint64_t ins1_enb:1;
-+              uint64_t ins0_enb:1;
-+              uint64_t reserved_44_45:2;
-+              uint64_t ins1_64b:1;
-+              uint64_t ins0_64b:1;
-+              uint64_t pci_wdis:1;
-+              uint64_t wait_com:1;
-+              uint64_t reserved_37_39:3;
-+              uint64_t max_word:5;
-+              uint64_t reserved_10_31:22;
-+              uint64_t timer:10;
-+      } cn31xx;
-+      struct cvmx_npi_ctl_status_s cn38xx;
-+      struct cvmx_npi_ctl_status_s cn38xxp2;
-+      struct cvmx_npi_ctl_status_cn31xx cn50xx;
-+      struct cvmx_npi_ctl_status_s cn58xx;
-+      struct cvmx_npi_ctl_status_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dbg_select {
-+      uint64_t u64;
-+      struct cvmx_npi_dbg_select_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t dbg_sel:16;
-+      } s;
-+      struct cvmx_npi_dbg_select_s cn30xx;
-+      struct cvmx_npi_dbg_select_s cn31xx;
-+      struct cvmx_npi_dbg_select_s cn38xx;
-+      struct cvmx_npi_dbg_select_s cn38xxp2;
-+      struct cvmx_npi_dbg_select_s cn50xx;
-+      struct cvmx_npi_dbg_select_s cn58xx;
-+      struct cvmx_npi_dbg_select_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dma_control {
-+      uint64_t u64;
-+      struct cvmx_npi_dma_control_s {
-+              uint64_t reserved_36_63:28;
-+              uint64_t b0_lend:1;
-+              uint64_t dwb_denb:1;
-+              uint64_t dwb_ichk:9;
-+              uint64_t fpa_que:3;
-+              uint64_t o_add1:1;
-+              uint64_t o_ro:1;
-+              uint64_t o_ns:1;
-+              uint64_t o_es:2;
-+              uint64_t o_mode:1;
-+              uint64_t hp_enb:1;
-+              uint64_t lp_enb:1;
-+              uint64_t csize:14;
-+      } s;
-+      struct cvmx_npi_dma_control_s cn30xx;
-+      struct cvmx_npi_dma_control_s cn31xx;
-+      struct cvmx_npi_dma_control_s cn38xx;
-+      struct cvmx_npi_dma_control_s cn38xxp2;
-+      struct cvmx_npi_dma_control_s cn50xx;
-+      struct cvmx_npi_dma_control_s cn58xx;
-+      struct cvmx_npi_dma_control_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dma_highp_counts {
-+      uint64_t u64;
-+      struct cvmx_npi_dma_highp_counts_s {
-+              uint64_t reserved_39_63:25;
-+              uint64_t fcnt:7;
-+              uint64_t dbell:32;
-+      } s;
-+      struct cvmx_npi_dma_highp_counts_s cn30xx;
-+      struct cvmx_npi_dma_highp_counts_s cn31xx;
-+      struct cvmx_npi_dma_highp_counts_s cn38xx;
-+      struct cvmx_npi_dma_highp_counts_s cn38xxp2;
-+      struct cvmx_npi_dma_highp_counts_s cn50xx;
-+      struct cvmx_npi_dma_highp_counts_s cn58xx;
-+      struct cvmx_npi_dma_highp_counts_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dma_highp_naddr {
-+      uint64_t u64;
-+      struct cvmx_npi_dma_highp_naddr_s {
-+              uint64_t reserved_40_63:24;
-+              uint64_t state:4;
-+              uint64_t addr:36;
-+      } s;
-+      struct cvmx_npi_dma_highp_naddr_s cn30xx;
-+      struct cvmx_npi_dma_highp_naddr_s cn31xx;
-+      struct cvmx_npi_dma_highp_naddr_s cn38xx;
-+      struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
-+      struct cvmx_npi_dma_highp_naddr_s cn50xx;
-+      struct cvmx_npi_dma_highp_naddr_s cn58xx;
-+      struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dma_lowp_counts {
-+      uint64_t u64;
-+      struct cvmx_npi_dma_lowp_counts_s {
-+              uint64_t reserved_39_63:25;
-+              uint64_t fcnt:7;
-+              uint64_t dbell:32;
-+      } s;
-+      struct cvmx_npi_dma_lowp_counts_s cn30xx;
-+      struct cvmx_npi_dma_lowp_counts_s cn31xx;
-+      struct cvmx_npi_dma_lowp_counts_s cn38xx;
-+      struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
-+      struct cvmx_npi_dma_lowp_counts_s cn50xx;
-+      struct cvmx_npi_dma_lowp_counts_s cn58xx;
-+      struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
-+};
-+
-+union cvmx_npi_dma_lowp_naddr {
-+      uint64_t u64;
-+      struct cvmx_npi_dma_lowp_naddr_s {
-+              uint64_t reserved_40_63:24;
-+              uint64_t state:4;
-+              uint64_t addr:36;
-+      } s;
-+      struct cvmx_npi_dma_lowp_naddr_s cn30xx;
-+      struct cvmx_npi_dma_lowp_naddr_s cn31xx;
-+      struct cvmx_npi_dma_lowp_naddr_s cn38xx;
-+      struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
-+      struct cvmx_npi_dma_lowp_naddr_s cn50xx;
-+      struct cvmx_npi_dma_lowp_naddr_s cn58xx;
-+      struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_highp_dbell {
-+      uint64_t u64;
-+      struct cvmx_npi_highp_dbell_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t dbell:16;
-+      } s;
-+      struct cvmx_npi_highp_dbell_s cn30xx;
-+      struct cvmx_npi_highp_dbell_s cn31xx;
-+      struct cvmx_npi_highp_dbell_s cn38xx;
-+      struct cvmx_npi_highp_dbell_s cn38xxp2;
-+      struct cvmx_npi_highp_dbell_s cn50xx;
-+      struct cvmx_npi_highp_dbell_s cn58xx;
-+      struct cvmx_npi_highp_dbell_s cn58xxp1;
-+};
-+
-+union cvmx_npi_highp_ibuff_saddr {
-+      uint64_t u64;
-+      struct cvmx_npi_highp_ibuff_saddr_s {
-+              uint64_t reserved_36_63:28;
-+              uint64_t saddr:36;
-+      } s;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
-+      struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_input_control {
-+      uint64_t u64;
-+      struct cvmx_npi_input_control_s {
-+              uint64_t reserved_23_63:41;
-+              uint64_t pkt_rr:1;
-+              uint64_t pbp_dhi:13;
-+              uint64_t d_nsr:1;
-+              uint64_t d_esr:2;
-+              uint64_t d_ror:1;
-+              uint64_t use_csr:1;
-+              uint64_t nsr:1;
-+              uint64_t esr:2;
-+              uint64_t ror:1;
-+      } s;
-+      struct cvmx_npi_input_control_cn30xx {
-+              uint64_t reserved_22_63:42;
-+              uint64_t pbp_dhi:13;
-+              uint64_t d_nsr:1;
-+              uint64_t d_esr:2;
-+              uint64_t d_ror:1;
-+              uint64_t use_csr:1;
-+              uint64_t nsr:1;
-+              uint64_t esr:2;
-+              uint64_t ror:1;
-+      } cn30xx;
-+      struct cvmx_npi_input_control_cn30xx cn31xx;
-+      struct cvmx_npi_input_control_s cn38xx;
-+      struct cvmx_npi_input_control_cn30xx cn38xxp2;
-+      struct cvmx_npi_input_control_s cn50xx;
-+      struct cvmx_npi_input_control_s cn58xx;
-+      struct cvmx_npi_input_control_s cn58xxp1;
-+};
-+
-+union cvmx_npi_int_enb {
-+      uint64_t u64;
-+      struct cvmx_npi_int_enb_s {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t i3_pperr:1;
-+              uint64_t i2_pperr:1;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t p3_ptout:1;
-+              uint64_t p2_ptout:1;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t p3_pperr:1;
-+              uint64_t p2_pperr:1;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t g3_rtout:1;
-+              uint64_t g2_rtout:1;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t p3_perr:1;
-+              uint64_t p2_perr:1;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t p3_rtout:1;
-+              uint64_t p2_rtout:1;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t i3_overf:1;
-+              uint64_t i2_overf:1;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t i3_rtout:1;
-+              uint64_t i2_rtout:1;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t po3_2sml:1;
-+              uint64_t po2_2sml:1;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npi_int_enb_cn30xx {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t reserved_36_38:3;
-+              uint64_t i0_pperr:1;
-+              uint64_t reserved_32_34:3;
-+              uint64_t p0_ptout:1;
-+              uint64_t reserved_28_30:3;
-+              uint64_t p0_pperr:1;
-+              uint64_t reserved_24_26:3;
-+              uint64_t g0_rtout:1;
-+              uint64_t reserved_20_22:3;
-+              uint64_t p0_perr:1;
-+              uint64_t reserved_16_18:3;
-+              uint64_t p0_rtout:1;
-+              uint64_t reserved_12_14:3;
-+              uint64_t i0_overf:1;
-+              uint64_t reserved_8_10:3;
-+              uint64_t i0_rtout:1;
-+              uint64_t reserved_4_6:3;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn30xx;
-+      struct cvmx_npi_int_enb_cn31xx {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t reserved_37_38:2;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t reserved_33_34:2;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t reserved_29_30:2;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t reserved_25_26:2;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t reserved_21_22:2;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t reserved_17_18:2;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t reserved_13_14:2;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t reserved_9_10:2;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t reserved_5_6:2;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn31xx;
-+      struct cvmx_npi_int_enb_s cn38xx;
-+      struct cvmx_npi_int_enb_cn38xxp2 {
-+              uint64_t reserved_42_63:22;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t i3_pperr:1;
-+              uint64_t i2_pperr:1;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t p3_ptout:1;
-+              uint64_t p2_ptout:1;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t p3_pperr:1;
-+              uint64_t p2_pperr:1;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t g3_rtout:1;
-+              uint64_t g2_rtout:1;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t p3_perr:1;
-+              uint64_t p2_perr:1;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t p3_rtout:1;
-+              uint64_t p2_rtout:1;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t i3_overf:1;
-+              uint64_t i2_overf:1;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t i3_rtout:1;
-+              uint64_t i2_rtout:1;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t po3_2sml:1;
-+              uint64_t po2_2sml:1;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn38xxp2;
-+      struct cvmx_npi_int_enb_cn31xx cn50xx;
-+      struct cvmx_npi_int_enb_s cn58xx;
-+      struct cvmx_npi_int_enb_s cn58xxp1;
-+};
-+
-+union cvmx_npi_int_sum {
-+      uint64_t u64;
-+      struct cvmx_npi_int_sum_s {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t i3_pperr:1;
-+              uint64_t i2_pperr:1;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t p3_ptout:1;
-+              uint64_t p2_ptout:1;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t p3_pperr:1;
-+              uint64_t p2_pperr:1;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t g3_rtout:1;
-+              uint64_t g2_rtout:1;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t p3_perr:1;
-+              uint64_t p2_perr:1;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t p3_rtout:1;
-+              uint64_t p2_rtout:1;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t i3_overf:1;
-+              uint64_t i2_overf:1;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t i3_rtout:1;
-+              uint64_t i2_rtout:1;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t po3_2sml:1;
-+              uint64_t po2_2sml:1;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } s;
-+      struct cvmx_npi_int_sum_cn30xx {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t reserved_36_38:3;
-+              uint64_t i0_pperr:1;
-+              uint64_t reserved_32_34:3;
-+              uint64_t p0_ptout:1;
-+              uint64_t reserved_28_30:3;
-+              uint64_t p0_pperr:1;
-+              uint64_t reserved_24_26:3;
-+              uint64_t g0_rtout:1;
-+              uint64_t reserved_20_22:3;
-+              uint64_t p0_perr:1;
-+              uint64_t reserved_16_18:3;
-+              uint64_t p0_rtout:1;
-+              uint64_t reserved_12_14:3;
-+              uint64_t i0_overf:1;
-+              uint64_t reserved_8_10:3;
-+              uint64_t i0_rtout:1;
-+              uint64_t reserved_4_6:3;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn30xx;
-+      struct cvmx_npi_int_sum_cn31xx {
-+              uint64_t reserved_62_63:2;
-+              uint64_t q1_a_f:1;
-+              uint64_t q1_s_e:1;
-+              uint64_t pdf_p_f:1;
-+              uint64_t pdf_p_e:1;
-+              uint64_t pcf_p_f:1;
-+              uint64_t pcf_p_e:1;
-+              uint64_t rdx_s_e:1;
-+              uint64_t rwx_s_e:1;
-+              uint64_t pnc_a_f:1;
-+              uint64_t pnc_s_e:1;
-+              uint64_t com_a_f:1;
-+              uint64_t com_s_e:1;
-+              uint64_t q3_a_f:1;
-+              uint64_t q3_s_e:1;
-+              uint64_t q2_a_f:1;
-+              uint64_t q2_s_e:1;
-+              uint64_t pcr_a_f:1;
-+              uint64_t pcr_s_e:1;
-+              uint64_t fcr_a_f:1;
-+              uint64_t fcr_s_e:1;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t reserved_37_38:2;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t reserved_33_34:2;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t reserved_29_30:2;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t reserved_25_26:2;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t reserved_21_22:2;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t reserved_17_18:2;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t reserved_13_14:2;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t reserved_9_10:2;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t reserved_5_6:2;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn31xx;
-+      struct cvmx_npi_int_sum_s cn38xx;
-+      struct cvmx_npi_int_sum_cn38xxp2 {
-+              uint64_t reserved_42_63:22;
-+              uint64_t iobdma:1;
-+              uint64_t p_dperr:1;
-+              uint64_t win_rto:1;
-+              uint64_t i3_pperr:1;
-+              uint64_t i2_pperr:1;
-+              uint64_t i1_pperr:1;
-+              uint64_t i0_pperr:1;
-+              uint64_t p3_ptout:1;
-+              uint64_t p2_ptout:1;
-+              uint64_t p1_ptout:1;
-+              uint64_t p0_ptout:1;
-+              uint64_t p3_pperr:1;
-+              uint64_t p2_pperr:1;
-+              uint64_t p1_pperr:1;
-+              uint64_t p0_pperr:1;
-+              uint64_t g3_rtout:1;
-+              uint64_t g2_rtout:1;
-+              uint64_t g1_rtout:1;
-+              uint64_t g0_rtout:1;
-+              uint64_t p3_perr:1;
-+              uint64_t p2_perr:1;
-+              uint64_t p1_perr:1;
-+              uint64_t p0_perr:1;
-+              uint64_t p3_rtout:1;
-+              uint64_t p2_rtout:1;
-+              uint64_t p1_rtout:1;
-+              uint64_t p0_rtout:1;
-+              uint64_t i3_overf:1;
-+              uint64_t i2_overf:1;
-+              uint64_t i1_overf:1;
-+              uint64_t i0_overf:1;
-+              uint64_t i3_rtout:1;
-+              uint64_t i2_rtout:1;
-+              uint64_t i1_rtout:1;
-+              uint64_t i0_rtout:1;
-+              uint64_t po3_2sml:1;
-+              uint64_t po2_2sml:1;
-+              uint64_t po1_2sml:1;
-+              uint64_t po0_2sml:1;
-+              uint64_t pci_rsl:1;
-+              uint64_t rml_wto:1;
-+              uint64_t rml_rto:1;
-+      } cn38xxp2;
-+      struct cvmx_npi_int_sum_cn31xx cn50xx;
-+      struct cvmx_npi_int_sum_s cn58xx;
-+      struct cvmx_npi_int_sum_s cn58xxp1;
-+};
-+
-+union cvmx_npi_lowp_dbell {
-+      uint64_t u64;
-+      struct cvmx_npi_lowp_dbell_s {
-+              uint64_t reserved_16_63:48;
-+              uint64_t dbell:16;
-+      } s;
-+      struct cvmx_npi_lowp_dbell_s cn30xx;
-+      struct cvmx_npi_lowp_dbell_s cn31xx;
-+      struct cvmx_npi_lowp_dbell_s cn38xx;
-+      struct cvmx_npi_lowp_dbell_s cn38xxp2;
-+      struct cvmx_npi_lowp_dbell_s cn50xx;
-+      struct cvmx_npi_lowp_dbell_s cn58xx;
-+      struct cvmx_npi_lowp_dbell_s cn58xxp1;
-+};
-+
-+union cvmx_npi_lowp_ibuff_saddr {
-+      uint64_t u64;
-+      struct cvmx_npi_lowp_ibuff_saddr_s {
-+              uint64_t reserved_36_63:28;
-+              uint64_t saddr:36;
-+      } s;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
-+      struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_mem_access_subidx {
-+      uint64_t u64;
-+      struct cvmx_npi_mem_access_subidx_s {
-+              uint64_t reserved_38_63:26;
-+              uint64_t shortl:1;
-+              uint64_t nmerge:1;
-+              uint64_t esr:2;
-+              uint64_t esw:2;
-+              uint64_t nsr:1;
-+              uint64_t nsw:1;
-+              uint64_t ror:1;
-+              uint64_t row:1;
-+              uint64_t ba:28;
-+      } s;
-+      struct cvmx_npi_mem_access_subidx_s cn30xx;
-+      struct cvmx_npi_mem_access_subidx_cn31xx {
-+              uint64_t reserved_36_63:28;
-+              uint64_t esr:2;
-+              uint64_t esw:2;
-+              uint64_t nsr:1;
-+              uint64_t nsw:1;
-+              uint64_t ror:1;
-+              uint64_t row:1;
-+              uint64_t ba:28;
-+      } cn31xx;
-+      struct cvmx_npi_mem_access_subidx_s cn38xx;
-+      struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
-+      struct cvmx_npi_mem_access_subidx_s cn50xx;
-+      struct cvmx_npi_mem_access_subidx_s cn58xx;
-+      struct cvmx_npi_mem_access_subidx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_msi_rcv {
-+      uint64_t u64;
-+      struct cvmx_npi_msi_rcv_s {
-+              uint64_t int_vec:64;
-+      } s;
-+      struct cvmx_npi_msi_rcv_s cn30xx;
-+      struct cvmx_npi_msi_rcv_s cn31xx;
-+      struct cvmx_npi_msi_rcv_s cn38xx;
-+      struct cvmx_npi_msi_rcv_s cn38xxp2;
-+      struct cvmx_npi_msi_rcv_s cn50xx;
-+      struct cvmx_npi_msi_rcv_s cn58xx;
-+      struct cvmx_npi_msi_rcv_s cn58xxp1;
-+};
-+
-+union cvmx_npi_num_desc_outputx {
-+      uint64_t u64;
-+      struct cvmx_npi_num_desc_outputx_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t size:32;
-+      } s;
-+      struct cvmx_npi_num_desc_outputx_s cn30xx;
-+      struct cvmx_npi_num_desc_outputx_s cn31xx;
-+      struct cvmx_npi_num_desc_outputx_s cn38xx;
-+      struct cvmx_npi_num_desc_outputx_s cn38xxp2;
-+      struct cvmx_npi_num_desc_outputx_s cn50xx;
-+      struct cvmx_npi_num_desc_outputx_s cn58xx;
-+      struct cvmx_npi_num_desc_outputx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_output_control {
-+      uint64_t u64;
-+      struct cvmx_npi_output_control_s {
-+              uint64_t reserved_49_63:15;
-+              uint64_t pkt_rr:1;
-+              uint64_t p3_bmode:1;
-+              uint64_t p2_bmode:1;
-+              uint64_t p1_bmode:1;
-+              uint64_t p0_bmode:1;
-+              uint64_t o3_es:2;
-+              uint64_t o3_ns:1;
-+              uint64_t o3_ro:1;
-+              uint64_t o2_es:2;
-+              uint64_t o2_ns:1;
-+              uint64_t o2_ro:1;
-+              uint64_t o1_es:2;
-+              uint64_t o1_ns:1;
-+              uint64_t o1_ro:1;
-+              uint64_t o0_es:2;
-+              uint64_t o0_ns:1;
-+              uint64_t o0_ro:1;
-+              uint64_t o3_csrm:1;
-+              uint64_t o2_csrm:1;
-+              uint64_t o1_csrm:1;
-+              uint64_t o0_csrm:1;
-+              uint64_t reserved_20_23:4;
-+              uint64_t iptr_o3:1;
-+              uint64_t iptr_o2:1;
-+              uint64_t iptr_o1:1;
-+              uint64_t iptr_o0:1;
-+              uint64_t esr_sl3:2;
-+              uint64_t nsr_sl3:1;
-+              uint64_t ror_sl3:1;
-+              uint64_t esr_sl2:2;
-+              uint64_t nsr_sl2:1;
-+              uint64_t ror_sl2:1;
-+              uint64_t esr_sl1:2;
-+              uint64_t nsr_sl1:1;
-+              uint64_t ror_sl1:1;
-+              uint64_t esr_sl0:2;
-+              uint64_t nsr_sl0:1;
-+              uint64_t ror_sl0:1;
-+      } s;
-+      struct cvmx_npi_output_control_cn30xx {
-+              uint64_t reserved_45_63:19;
-+              uint64_t p0_bmode:1;
-+              uint64_t reserved_32_43:12;
-+              uint64_t o0_es:2;
-+              uint64_t o0_ns:1;
-+              uint64_t o0_ro:1;
-+              uint64_t reserved_25_27:3;
-+              uint64_t o0_csrm:1;
-+              uint64_t reserved_17_23:7;
-+              uint64_t iptr_o0:1;
-+              uint64_t reserved_4_15:12;
-+              uint64_t esr_sl0:2;
-+              uint64_t nsr_sl0:1;
-+              uint64_t ror_sl0:1;
-+      } cn30xx;
-+      struct cvmx_npi_output_control_cn31xx {
-+              uint64_t reserved_46_63:18;
-+              uint64_t p1_bmode:1;
-+              uint64_t p0_bmode:1;
-+              uint64_t reserved_36_43:8;
-+              uint64_t o1_es:2;
-+              uint64_t o1_ns:1;
-+              uint64_t o1_ro:1;
-+              uint64_t o0_es:2;
-+              uint64_t o0_ns:1;
-+              uint64_t o0_ro:1;
-+              uint64_t reserved_26_27:2;
-+              uint64_t o1_csrm:1;
-+              uint64_t o0_csrm:1;
-+              uint64_t reserved_18_23:6;
-+              uint64_t iptr_o1:1;
-+              uint64_t iptr_o0:1;
-+              uint64_t reserved_8_15:8;
-+              uint64_t esr_sl1:2;
-+              uint64_t nsr_sl1:1;
-+              uint64_t ror_sl1:1;
-+              uint64_t esr_sl0:2;
-+              uint64_t nsr_sl0:1;
-+              uint64_t ror_sl0:1;
-+      } cn31xx;
-+      struct cvmx_npi_output_control_s cn38xx;
-+      struct cvmx_npi_output_control_cn38xxp2 {
-+              uint64_t reserved_48_63:16;
-+              uint64_t p3_bmode:1;
-+              uint64_t p2_bmode:1;
-+              uint64_t p1_bmode:1;
-+              uint64_t p0_bmode:1;
-+              uint64_t o3_es:2;
-+              uint64_t o3_ns:1;
-+              uint64_t o3_ro:1;
-+              uint64_t o2_es:2;
-+              uint64_t o2_ns:1;
-+              uint64_t o2_ro:1;
-+              uint64_t o1_es:2;
-+              uint64_t o1_ns:1;
-+              uint64_t o1_ro:1;
-+              uint64_t o0_es:2;
-+              uint64_t o0_ns:1;
-+              uint64_t o0_ro:1;
-+              uint64_t o3_csrm:1;
-+              uint64_t o2_csrm:1;
-+              uint64_t o1_csrm:1;
-+              uint64_t o0_csrm:1;
-+              uint64_t reserved_20_23:4;
-+              uint64_t iptr_o3:1;
-+              uint64_t iptr_o2:1;
-+              uint64_t iptr_o1:1;
-+              uint64_t iptr_o0:1;
-+              uint64_t esr_sl3:2;
-+              uint64_t nsr_sl3:1;
-+              uint64_t ror_sl3:1;
-+              uint64_t esr_sl2:2;
-+              uint64_t nsr_sl2:1;
-+              uint64_t ror_sl2:1;
-+              uint64_t esr_sl1:2;
-+              uint64_t nsr_sl1:1;
-+              uint64_t ror_sl1:1;
-+              uint64_t esr_sl0:2;
-+              uint64_t nsr_sl0:1;
-+              uint64_t ror_sl0:1;
-+      } cn38xxp2;
-+      struct cvmx_npi_output_control_cn50xx {
-+              uint64_t reserved_49_63:15;
-+              uint64_t pkt_rr:1;
-+              uint64_t reserved_46_47:2;
-+              uint64_t p1_bmode:1;
-+              uint64_t p0_bmode:1;
-+              uint64_t reserved_36_43:8;
-+              uint64_t o1_es:2;
-+              uint64_t o1_ns:1;
-+              uint64_t o1_ro:1;
-+              uint64_t o0_es:2;
-+              uint64_t o0_ns:1;
-+              uint64_t o0_ro:1;
-+              uint64_t reserved_26_27:2;
-+              uint64_t o1_csrm:1;
-+              uint64_t o0_csrm:1;
-+              uint64_t reserved_18_23:6;
-+              uint64_t iptr_o1:1;
-+              uint64_t iptr_o0:1;
-+              uint64_t reserved_8_15:8;
-+              uint64_t esr_sl1:2;
-+              uint64_t nsr_sl1:1;
-+              uint64_t ror_sl1:1;
-+              uint64_t esr_sl0:2;
-+              uint64_t nsr_sl0:1;
-+              uint64_t ror_sl0:1;
-+      } cn50xx;
-+      struct cvmx_npi_output_control_s cn58xx;
-+      struct cvmx_npi_output_control_s cn58xxp1;
-+};
-+
-+union cvmx_npi_px_dbpair_addr {
-+      uint64_t u64;
-+      struct cvmx_npi_px_dbpair_addr_s {
-+              uint64_t reserved_63_63:1;
-+              uint64_t state:2;
-+              uint64_t naddr:61;
-+      } s;
-+      struct cvmx_npi_px_dbpair_addr_s cn30xx;
-+      struct cvmx_npi_px_dbpair_addr_s cn31xx;
-+      struct cvmx_npi_px_dbpair_addr_s cn38xx;
-+      struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
-+      struct cvmx_npi_px_dbpair_addr_s cn50xx;
-+      struct cvmx_npi_px_dbpair_addr_s cn58xx;
-+      struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_px_instr_addr {
-+      uint64_t u64;
-+      struct cvmx_npi_px_instr_addr_s {
-+              uint64_t state:3;
-+              uint64_t naddr:61;
-+      } s;
-+      struct cvmx_npi_px_instr_addr_s cn30xx;
-+      struct cvmx_npi_px_instr_addr_s cn31xx;
-+      struct cvmx_npi_px_instr_addr_s cn38xx;
-+      struct cvmx_npi_px_instr_addr_s cn38xxp2;
-+      struct cvmx_npi_px_instr_addr_s cn50xx;
-+      struct cvmx_npi_px_instr_addr_s cn58xx;
-+      struct cvmx_npi_px_instr_addr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_px_instr_cnts {
-+      uint64_t u64;
-+      struct cvmx_npi_px_instr_cnts_s {
-+              uint64_t reserved_38_63:26;
-+              uint64_t fcnt:6;
-+              uint64_t avail:32;
-+      } s;
-+      struct cvmx_npi_px_instr_cnts_s cn30xx;
-+      struct cvmx_npi_px_instr_cnts_s cn31xx;
-+      struct cvmx_npi_px_instr_cnts_s cn38xx;
-+      struct cvmx_npi_px_instr_cnts_s cn38xxp2;
-+      struct cvmx_npi_px_instr_cnts_s cn50xx;
-+      struct cvmx_npi_px_instr_cnts_s cn58xx;
-+      struct cvmx_npi_px_instr_cnts_s cn58xxp1;
-+};
-+
-+union cvmx_npi_px_pair_cnts {
-+      uint64_t u64;
-+      struct cvmx_npi_px_pair_cnts_s {
-+              uint64_t reserved_37_63:27;
-+              uint64_t fcnt:5;
-+              uint64_t avail:32;
-+      } s;
-+      struct cvmx_npi_px_pair_cnts_s cn30xx;
-+      struct cvmx_npi_px_pair_cnts_s cn31xx;
-+      struct cvmx_npi_px_pair_cnts_s cn38xx;
-+      struct cvmx_npi_px_pair_cnts_s cn38xxp2;
-+      struct cvmx_npi_px_pair_cnts_s cn50xx;
-+      struct cvmx_npi_px_pair_cnts_s cn58xx;
-+      struct cvmx_npi_px_pair_cnts_s cn58xxp1;
-+};
-+
-+union cvmx_npi_pci_burst_size {
-+      uint64_t u64;
-+      struct cvmx_npi_pci_burst_size_s {
-+              uint64_t reserved_14_63:50;
-+              uint64_t wr_brst:7;
-+              uint64_t rd_brst:7;
-+      } s;
-+      struct cvmx_npi_pci_burst_size_s cn30xx;
-+      struct cvmx_npi_pci_burst_size_s cn31xx;
-+      struct cvmx_npi_pci_burst_size_s cn38xx;
-+      struct cvmx_npi_pci_burst_size_s cn38xxp2;
-+      struct cvmx_npi_pci_burst_size_s cn50xx;
-+      struct cvmx_npi_pci_burst_size_s cn58xx;
-+      struct cvmx_npi_pci_burst_size_s cn58xxp1;
-+};
-+
-+union cvmx_npi_pci_int_arb_cfg {
-+      uint64_t u64;
-+      struct cvmx_npi_pci_int_arb_cfg_s {
-+              uint64_t reserved_13_63:51;
-+              uint64_t hostmode:1;
-+              uint64_t pci_ovr:4;
-+              uint64_t reserved_5_7:3;
-+              uint64_t en:1;
-+              uint64_t park_mod:1;
-+              uint64_t park_dev:3;
-+      } s;
-+      struct cvmx_npi_pci_int_arb_cfg_cn30xx {
-+              uint64_t reserved_5_63:59;
-+              uint64_t en:1;
-+              uint64_t park_mod:1;
-+              uint64_t park_dev:3;
-+      } cn30xx;
-+      struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
-+      struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
-+      struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
-+      struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
-+      struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
-+      struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
-+};
-+
-+union cvmx_npi_pci_read_cmd {
-+      uint64_t u64;
-+      struct cvmx_npi_pci_read_cmd_s {
-+              uint64_t reserved_11_63:53;
-+              uint64_t cmd_size:11;
-+      } s;
-+      struct cvmx_npi_pci_read_cmd_s cn30xx;
-+      struct cvmx_npi_pci_read_cmd_s cn31xx;
-+      struct cvmx_npi_pci_read_cmd_s cn38xx;
-+      struct cvmx_npi_pci_read_cmd_s cn38xxp2;
-+      struct cvmx_npi_pci_read_cmd_s cn50xx;
-+      struct cvmx_npi_pci_read_cmd_s cn58xx;
-+      struct cvmx_npi_pci_read_cmd_s cn58xxp1;
-+};
-+
-+union cvmx_npi_port32_instr_hdr {
-+      uint64_t u64;
-+      struct cvmx_npi_port32_instr_hdr_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t pbp:1;
-+              uint64_t rsv_f:5;
-+              uint64_t rparmode:2;
-+              uint64_t rsv_e:1;
-+              uint64_t rskp_len:7;
-+              uint64_t rsv_d:6;
-+              uint64_t use_ihdr:1;
-+              uint64_t rsv_c:5;
-+              uint64_t par_mode:2;
-+              uint64_t rsv_b:1;
-+              uint64_t skp_len:7;
-+              uint64_t rsv_a:6;
-+      } s;
-+      struct cvmx_npi_port32_instr_hdr_s cn30xx;
-+      struct cvmx_npi_port32_instr_hdr_s cn31xx;
-+      struct cvmx_npi_port32_instr_hdr_s cn38xx;
-+      struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
-+      struct cvmx_npi_port32_instr_hdr_s cn50xx;
-+      struct cvmx_npi_port32_instr_hdr_s cn58xx;
-+      struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_port33_instr_hdr {
-+      uint64_t u64;
-+      struct cvmx_npi_port33_instr_hdr_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t pbp:1;
-+              uint64_t rsv_f:5;
-+              uint64_t rparmode:2;
-+              uint64_t rsv_e:1;
-+              uint64_t rskp_len:7;
-+              uint64_t rsv_d:6;
-+              uint64_t use_ihdr:1;
-+              uint64_t rsv_c:5;
-+              uint64_t par_mode:2;
-+              uint64_t rsv_b:1;
-+              uint64_t skp_len:7;
-+              uint64_t rsv_a:6;
-+      } s;
-+      struct cvmx_npi_port33_instr_hdr_s cn31xx;
-+      struct cvmx_npi_port33_instr_hdr_s cn38xx;
-+      struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
-+      struct cvmx_npi_port33_instr_hdr_s cn50xx;
-+      struct cvmx_npi_port33_instr_hdr_s cn58xx;
-+      struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_port34_instr_hdr {
-+      uint64_t u64;
-+      struct cvmx_npi_port34_instr_hdr_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t pbp:1;
-+              uint64_t rsv_f:5;
-+              uint64_t rparmode:2;
-+              uint64_t rsv_e:1;
-+              uint64_t rskp_len:7;
-+              uint64_t rsv_d:6;
-+              uint64_t use_ihdr:1;
-+              uint64_t rsv_c:5;
-+              uint64_t par_mode:2;
-+              uint64_t rsv_b:1;
-+              uint64_t skp_len:7;
-+              uint64_t rsv_a:6;
-+      } s;
-+      struct cvmx_npi_port34_instr_hdr_s cn38xx;
-+      struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
-+      struct cvmx_npi_port34_instr_hdr_s cn58xx;
-+      struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_port35_instr_hdr {
-+      uint64_t u64;
-+      struct cvmx_npi_port35_instr_hdr_s {
-+              uint64_t reserved_44_63:20;
-+              uint64_t pbp:1;
-+              uint64_t rsv_f:5;
-+              uint64_t rparmode:2;
-+              uint64_t rsv_e:1;
-+              uint64_t rskp_len:7;
-+              uint64_t rsv_d:6;
-+              uint64_t use_ihdr:1;
-+              uint64_t rsv_c:5;
-+              uint64_t par_mode:2;
-+              uint64_t rsv_b:1;
-+              uint64_t skp_len:7;
-+              uint64_t rsv_a:6;
-+      } s;
-+      struct cvmx_npi_port35_instr_hdr_s cn38xx;
-+      struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
-+      struct cvmx_npi_port35_instr_hdr_s cn58xx;
-+      struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
-+};
-+
-+union cvmx_npi_port_bp_control {
-+      uint64_t u64;
-+      struct cvmx_npi_port_bp_control_s {
-+              uint64_t reserved_8_63:56;
-+              uint64_t bp_on:4;
-+              uint64_t enb:4;
-+      } s;
-+      struct cvmx_npi_port_bp_control_s cn30xx;
-+      struct cvmx_npi_port_bp_control_s cn31xx;
-+      struct cvmx_npi_port_bp_control_s cn38xx;
-+      struct cvmx_npi_port_bp_control_s cn38xxp2;
-+      struct cvmx_npi_port_bp_control_s cn50xx;
-+      struct cvmx_npi_port_bp_control_s cn58xx;
-+      struct cvmx_npi_port_bp_control_s cn58xxp1;
-+};
-+
-+union cvmx_npi_rsl_int_blocks {
-+      uint64_t u64;
-+      struct cvmx_npi_rsl_int_blocks_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t rint_31:1;
-+              uint64_t iob:1;
-+              uint64_t reserved_28_29:2;
-+              uint64_t rint_27:1;
-+              uint64_t rint_26:1;
-+              uint64_t rint_25:1;
-+              uint64_t rint_24:1;
-+              uint64_t asx1:1;
-+              uint64_t asx0:1;
-+              uint64_t rint_21:1;
-+              uint64_t pip:1;
-+              uint64_t spx1:1;
-+              uint64_t spx0:1;
-+              uint64_t lmc:1;
-+              uint64_t l2c:1;
-+              uint64_t rint_15:1;
-+              uint64_t reserved_13_14:2;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t rint_8:1;
-+              uint64_t zip:1;
-+              uint64_t dfa:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npi:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } s;
-+      struct cvmx_npi_rsl_int_blocks_cn30xx {
-+              uint64_t reserved_32_63:32;
-+              uint64_t rint_31:1;
-+              uint64_t iob:1;
-+              uint64_t rint_29:1;
-+              uint64_t rint_28:1;
-+              uint64_t rint_27:1;
-+              uint64_t rint_26:1;
-+              uint64_t rint_25:1;
-+              uint64_t rint_24:1;
-+              uint64_t asx1:1;
-+              uint64_t asx0:1;
-+              uint64_t rint_21:1;
-+              uint64_t pip:1;
-+              uint64_t spx1:1;
-+              uint64_t spx0:1;
-+              uint64_t lmc:1;
-+              uint64_t l2c:1;
-+              uint64_t rint_15:1;
-+              uint64_t rint_14:1;
-+              uint64_t usb:1;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t rint_8:1;
-+              uint64_t zip:1;
-+              uint64_t dfa:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npi:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } cn30xx;
-+      struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
-+      struct cvmx_npi_rsl_int_blocks_cn38xx {
-+              uint64_t reserved_32_63:32;
-+              uint64_t rint_31:1;
-+              uint64_t iob:1;
-+              uint64_t rint_29:1;
-+              uint64_t rint_28:1;
-+              uint64_t rint_27:1;
-+              uint64_t rint_26:1;
-+              uint64_t rint_25:1;
-+              uint64_t rint_24:1;
-+              uint64_t asx1:1;
-+              uint64_t asx0:1;
-+              uint64_t rint_21:1;
-+              uint64_t pip:1;
-+              uint64_t spx1:1;
-+              uint64_t spx0:1;
-+              uint64_t lmc:1;
-+              uint64_t l2c:1;
-+              uint64_t rint_15:1;
-+              uint64_t rint_14:1;
-+              uint64_t rint_13:1;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t rint_8:1;
-+              uint64_t zip:1;
-+              uint64_t dfa:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npi:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } cn38xx;
-+      struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
-+      struct cvmx_npi_rsl_int_blocks_cn50xx {
-+              uint64_t reserved_31_63:33;
-+              uint64_t iob:1;
-+              uint64_t lmc1:1;
-+              uint64_t agl:1;
-+              uint64_t reserved_24_27:4;
-+              uint64_t asx1:1;
-+              uint64_t asx0:1;
-+              uint64_t reserved_21_21:1;
-+              uint64_t pip:1;
-+              uint64_t spx1:1;
-+              uint64_t spx0:1;
-+              uint64_t lmc:1;
-+              uint64_t l2c:1;
-+              uint64_t reserved_15_15:1;
-+              uint64_t rad:1;
-+              uint64_t usb:1;
-+              uint64_t pow:1;
-+              uint64_t tim:1;
-+              uint64_t pko:1;
-+              uint64_t ipd:1;
-+              uint64_t reserved_8_8:1;
-+              uint64_t zip:1;
-+              uint64_t dfa:1;
-+              uint64_t fpa:1;
-+              uint64_t key:1;
-+              uint64_t npi:1;
-+              uint64_t gmx1:1;
-+              uint64_t gmx0:1;
-+              uint64_t mio:1;
-+      } cn50xx;
-+      struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
-+      struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
-+};
-+
-+union cvmx_npi_size_inputx {
-+      uint64_t u64;
-+      struct cvmx_npi_size_inputx_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t size:32;
-+      } s;
-+      struct cvmx_npi_size_inputx_s cn30xx;
-+      struct cvmx_npi_size_inputx_s cn31xx;
-+      struct cvmx_npi_size_inputx_s cn38xx;
-+      struct cvmx_npi_size_inputx_s cn38xxp2;
-+      struct cvmx_npi_size_inputx_s cn50xx;
-+      struct cvmx_npi_size_inputx_s cn58xx;
-+      struct cvmx_npi_size_inputx_s cn58xxp1;
-+};
-+
-+union cvmx_npi_win_read_to {
-+      uint64_t u64;
-+      struct cvmx_npi_win_read_to_s {
-+              uint64_t reserved_32_63:32;
-+              uint64_t time:32;
-+      } s;
-+      struct cvmx_npi_win_read_to_s cn30xx;
-+      struct cvmx_npi_win_read_to_s cn31xx;
-+      struct cvmx_npi_win_read_to_s cn38xx;
-+      struct cvmx_npi_win_read_to_s cn38xxp2;
-+      struct cvmx_npi_win_read_to_s cn50xx;
-+      struct cvmx_npi_win_read_to_s cn58xx;
-+      struct cvmx_npi_win_read_to_s cn58xxp1;
-+};
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
-@@ -0,0 +1,1645 @@
-+/***********************license start***************
-+ * Author: Cavium Networks
-+ *
-+ * Contact: support@caviumnetworks.com
-+ * This file is part of the OCTEON SDK
-+ *
-+ * Copyright (c) 2003-2008 Cavium Networks
-+ *
-+ * This file is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License, Version 2, as
-+ * published by the Free Software Foundation.
-+ *
-+ * This file is distributed in the hope that it will be useful, but
-+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
-+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
-+ * NONINFRINGEMENT.  See the GNU General Public License for more
-+ * details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this file; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+ * or visit http://www.gnu.org/licenses/.
-+ *
-+ * This file may also be available under a different license from Cavium.
-+ * Contact Cavium Networks for more information
-+ ***********************license end**************************************/
-+
-+#ifndef __CVMX_PCI_DEFS_H__
-+#define __CVMX_PCI_DEFS_H__
-+
-+#define CVMX_PCI_BAR1_INDEXX(offset) \
-+       (0x0000000000000100ull + (((offset) & 31) * 4))
-+#define CVMX_PCI_BIST_REG \
-+       (0x00000000000001C0ull)
-+#define CVMX_PCI_CFG00 \
-+       (0x0000000000000000ull)
-+#define CVMX_PCI_CFG01 \
-+       (0x0000000000000004ull)
-+#define CVMX_PCI_CFG02 \
-+       (0x0000000000000008ull)
-+#define CVMX_PCI_CFG03 \
-+       (0x000000000000000Cull)
-+#define CVMX_PCI_CFG04 \
-+       (0x0000000000000010ull)
-+#define CVMX_PCI_CFG05 \
-+       (0x0000000000000014ull)
-+#define CVMX_PCI_CFG06 \
-+       (0x0000000000000018ull)
-+#define CVMX_PCI_CFG07 \
-+       (0x000000000000001Cull)
-+#define CVMX_PCI_CFG08 \
-+       (0x0000000000000020ull)
-+#define CVMX_PCI_CFG09 \
-+       (0x0000000000000024ull)
-+#define CVMX_PCI_CFG10 \
-+       (0x0000000000000028ull)
-+#define CVMX_PCI_CFG11 \
-+       (0x000000000000002Cull)
-+#define CVMX_PCI_CFG12 \
-+       (0x0000000000000030ull)
-+#define CVMX_PCI_CFG13 \
-+       (0x0000000000000034ull)
-+#define CVMX_PCI_CFG15 \
-+       (0x000000000000003Cull)
-+#define CVMX_PCI_CFG16 \
-+       (0x0000000000000040ull)
-+#define CVMX_PCI_CFG17 \
-+       (0x0000000000000044ull)
-+#define CVMX_PCI_CFG18 \
-+       (0x0000000000000048ull)
-+#define CVMX_PCI_CFG19 \
-+       (0x000000000000004Cull)
-+#define CVMX_PCI_CFG20 \
-+       (0x0000000000000050ull)
-+#define CVMX_PCI_CFG21 \
-+       (0x0000000000000054ull)
-+#define CVMX_PCI_CFG22 \
-+       (0x0000000000000058ull)
-+#define CVMX_PCI_CFG56 \
-+       (0x00000000000000E0ull)
-+#define CVMX_PCI_CFG57 \
-+       (0x00000000000000E4ull)
-+#define CVMX_PCI_CFG58 \
-+       (0x00000000000000E8ull)
-+#define CVMX_PCI_CFG59 \
-+       (0x00000000000000ECull)
-+#define CVMX_PCI_CFG60 \
-+       (0x00000000000000F0ull)
-+#define CVMX_PCI_CFG61 \
-+       (0x00000000000000F4ull)
-+#define CVMX_PCI_CFG62 \
-+       (0x00000000000000F8ull)
-+#define CVMX_PCI_CFG63 \
-+       (0x00000000000000FCull)
-+#define CVMX_PCI_CNT_REG \
-+       (0x00000000000001B8ull)
-+#define CVMX_PCI_CTL_STATUS_2 \
-+       (0x000000000000018Cull)
-+#define CVMX_PCI_DBELL_0 \
-+       (0x0000000000000080ull)
-+#define CVMX_PCI_DBELL_1 \
-+       (0x0000000000000088ull)
-+#define CVMX_PCI_DBELL_2 \
-+       (0x0000000000000090ull)
-+#define CVMX_PCI_DBELL_3 \
-+       (0x0000000000000098ull)
-+#define CVMX_PCI_DBELL_X(offset) \
-+       (0x0000000000000080ull + (((offset) & 3) * 8))
-+#define CVMX_PCI_DMA_CNT0 \
-+       (0x00000000000000A0ull)
-+#define CVMX_PCI_DMA_CNT1 \
-+       (0x00000000000000A8ull)
-+#define CVMX_PCI_DMA_CNTX(offset) \
-+       (0x00000000000000A0ull + (((offset) & 1) * 8))
-+#define CVMX_PCI_DMA_INT_LEV0 \
-+       (0x00000000000000A4ull)
-+#define CVMX_PCI_DMA_INT_LEV1 \
-+       (0x00000000000000ACull)
-+#define CVMX_PCI_DMA_INT_LEVX(offset) \
-+       (0x00000000000000A4ull + (((offset) & 1) * 8))
-+#define CVMX_PCI_DMA_TIME0 \
-+       (0x00000000000000B0ull)
-+#define CVMX_PCI_DMA_TIME1 \
-+       (0x00000000000000B4ull)
-+#define CVMX_PCI_DMA_TIMEX(offset) \
-+       (0x00000000000000B0ull + (((offset) & 1) * 4))
-+#define CVMX_PCI_INSTR_COUNT0 \
-+       (0x0000000000000084ull)
-+#define CVMX_PCI_INSTR_COUNT1 \
-+       (0x000000000000008Cull)
-+#define CVMX_PCI_INSTR_COUNT2 \
-+       (0x0000000000000094ull)
-+#define CVMX_PCI_INSTR_COUNT3 \
-+       (0x000000000000009Cull)
-+#define CVMX_PCI_INSTR_COUNTX(offset) \
-+       (0x0000000000000084ull + (((offset) & 3) * 8))
-+#define CVMX_PCI_INT_ENB \
-+       (0x0000000000000038ull)
-+#define CVMX_PCI_INT_ENB2 \
-+       (0x00000000000001A0ull)
-+#define CVMX_PCI_INT_SUM \
-+       (0x0000000000000030ull)
-+#define CVMX_PCI_INT_SUM2 \
-+       (0x0000000000000198ull)
-+#define CVMX_PCI_MSI_RCV \
-+       (0x00000000000000F0ull)
-+#define CVMX_PCI_PKTS_SENT0 \
-+       (0x0000000000000040ull)
-+#define CVMX_PCI_PKTS_SENT1 \
-+       (0x0000000000000050ull)
-+#define CVMX_PCI_PKTS_SENT2 \
-+       (0x0000000000000060ull)
-+#define CVMX_PCI_PKTS_SENT3 \
-+       (0x0000000000000070ull)
-+#define CVMX_PCI_PKTS_SENTX(offset) \
-+       (0x0000000000000040ull + (((offset) & 3) * 16))
-+#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
-+       (0x0000000000000048ull)
-+#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
-+       (0x0000000000000058ull)
-+#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
-+       (0x0000000000000068ull)
-+#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
-+       (0x0000000000000078ull)
-+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
-+       (0x0000000000000048ull + (((offset) & 3) * 16))
-+#define CVMX_PCI_PKTS_SENT_TIME0 \
-+       (0x000000000000004Cull)
-+#define CVMX_PCI_PKTS_SENT_TIME1 \
-+       (0x000000000000005Cull)
-+#define CVMX_PCI_PKTS_SENT_TIME2 \
-+       (0x000000000000006Cull)
-+#define CVMX_PCI_PKTS_SENT_TIME3 \
-+       (0x000000000000007Cull)
-+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
-+       (0x000000000000004Cull + (((offset) & 3) * 16))
-+#define CVMX_PCI_PKT_CREDITS0 \
-+       (0x0000000000000044ull)
-+#define CVMX_PCI_PKT_CREDITS1 \
-+       (0x0000000000000054ull)
-+#define CVMX_PCI_PKT_CREDITS2 \
-+       (0x0000000000000064ull)
-+#define CVMX_PCI_PKT_CREDITS3 \
-+       (0x0000000000000074ull)
-+#define CVMX_PCI_PKT_CREDITSX(offset) \
-+       (0x0000000000000044ull + (((offset) & 3) * 16))
-+#define CVMX_PCI_READ_CMD_6 \
-+       (0x0000000000000180ull)
-+#define CVMX_PCI_READ_CMD_C \
-+       (0x0000000000000184ull)
-+#define CVMX_PCI_READ_CMD_E \
-+       (0x0000000000000188ull)
-+#define CVMX_PCI_READ_TIMEOUT \
-+       CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
-+#define CVMX_PCI_SCM_REG \
-+       (0x00000000000001A8ull)
-+#define CVMX_PCI_TSR_REG \
-+       (0x00000000000001B0ull)
-+#define CVMX_PCI_WIN_RD_ADDR \
-+       (0x0000000000000008ull)
-+#define CVMX_PCI_WIN_RD_DATA \
-+       (0x0000000000000020ull)
-+#define CVMX_PCI_WIN_WR_ADDR \
-+       (0x0000000000000000ull)
-+#define CVMX_PCI_WIN_WR_DATA \
-+       (0x0000000000000010ull)
-+#define CVMX_PCI_WIN_WR_MASK \
-+       (0x0000000000000018ull)
-+
-+union cvmx_pci_bar1_indexx {
-+      uint32_t u32;
-+      struct cvmx_pci_bar1_indexx_s {
-+              uint32_t reserved_18_31:14;
-+              uint32_t addr_idx:14;
-+              uint32_t ca:1;
-+              uint32_t end_swp:2;
-+              uint32_t addr_v:1;
-+      } s;
-+      struct cvmx_pci_bar1_indexx_s cn30xx;
-+      struct cvmx_pci_bar1_indexx_s cn31xx;
-+      struct cvmx_pci_bar1_indexx_s cn38xx;
-+      struct cvmx_pci_bar1_indexx_s cn38xxp2;
-+      struct cvmx_pci_bar1_indexx_s cn50xx;
-+      struct cvmx_pci_bar1_indexx_s cn58xx;
-+      struct cvmx_pci_bar1_indexx_s cn58xxp1;
-+};
-+
-+union cvmx_pci_bist_reg {
-+      uint64_t u64;
-+      struct cvmx_pci_bist_reg_s {
-+              uint64_t reserved_10_63:54;
-+              uint64_t rsp_bs:1;
-+              uint64_t dma0_bs:1;
-+              uint64_t cmd0_bs:1;
-+              uint64_t cmd_bs:1;
-+              uint64_t csr2p_bs:1;
-+              uint64_t csrr_bs:1;
-+              uint64_t rsp2p_bs:1;
-+              uint64_t csr2n_bs:1;
-+              uint64_t dat2n_bs:1;
-+              uint64_t dbg2n_bs:1;
-+      } s;
-+      struct cvmx_pci_bist_reg_s cn50xx;
-+};
-+
-+union cvmx_pci_cfg00 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg00_s {
-+              uint32_t devid:16;
-+              uint32_t vendid:16;
-+      } s;
-+      struct cvmx_pci_cfg00_s cn30xx;
-+      struct cvmx_pci_cfg00_s cn31xx;
-+      struct cvmx_pci_cfg00_s cn38xx;
-+      struct cvmx_pci_cfg00_s cn38xxp2;
-+      struct cvmx_pci_cfg00_s cn50xx;
-+      struct cvmx_pci_cfg00_s cn58xx;
-+      struct cvmx_pci_cfg00_s cn58xxp1;
-+};
-+
-+union cvmx_pci_cfg01 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg01_s {
-+              uint32_t dpe:1;
-+              uint32_t sse:1;
-+              uint32_t rma:1;
-+              uint32_t rta:1;
-+              uint32_t sta:1;
-+              uint32_t devt:2;
-+              uint32_t mdpe:1;
-+              uint32_t fbb:1;
-+              uint32_t reserved_22_22:1;
-+              uint32_t m66:1;
-+              uint32_t cle:1;
-+              uint32_t i_stat:1;
-+              uint32_t reserved_11_18:8;
-+              uint32_t i_dis:1;
-+              uint32_t fbbe:1;
-+              uint32_t see:1;
-+              uint32_t ads:1;
-+              uint32_t pee:1;
-+              uint32_t vps:1;
-+              uint32_t mwice:1;
-+              uint32_t scse:1;
-+              uint32_t me:1;
-+              uint32_t msae:1;
-+              uint32_t isae:1;
-+      } s;
-+      struct cvmx_pci_cfg01_s cn30xx;
-+      struct cvmx_pci_cfg01_s cn31xx;
-+      struct cvmx_pci_cfg01_s cn38xx;
-+      struct cvmx_pci_cfg01_s cn38xxp2;
-+      struct cvmx_pci_cfg01_s cn50xx;
-+      struct cvmx_pci_cfg01_s cn58xx;
-+      struct cvmx_pci_cfg01_s cn58xxp1;
-+};
-+
-+union cvmx_pci_cfg02 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg02_s {
-+              uint32_t cc:24;
-+              uint32_t rid:8;
-+      } s;
-+      struct cvmx_pci_cfg02_s cn30xx;
-+      struct cvmx_pci_cfg02_s cn31xx;
-+      struct cvmx_pci_cfg02_s cn38xx;
-+      struct cvmx_pci_cfg02_s cn38xxp2;
-+      struct cvmx_pci_cfg02_s cn50xx;
-+      struct cvmx_pci_cfg02_s cn58xx;
-+      struct cvmx_pci_cfg02_s cn58xxp1;
-+};
-+
-+union cvmx_pci_cfg03 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg03_s {
-+              uint32_t bcap:1;
-+              uint32_t brb:1;
-+              uint32_t reserved_28_29:2;
-+              uint32_t bcod:4;
-+              uint32_t ht:8;
-+              uint32_t lt:8;
-+              uint32_t cls:8;
-+      } s;
-+      struct cvmx_pci_cfg03_s cn30xx;
-+      struct cvmx_pci_cfg03_s cn31xx;
-+      struct cvmx_pci_cfg03_s cn38xx;
-+      struct cvmx_pci_cfg03_s cn38xxp2;
-+      struct cvmx_pci_cfg03_s cn50xx;
-+      struct cvmx_pci_cfg03_s cn58xx;
-+      struct cvmx_pci_cfg03_s cn58xxp1;
-+};
-+
-+union cvmx_pci_cfg04 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg04_s {
-+              uint32_t lbase:20;
-+              uint32_t lbasez:8;
-+              uint32_t pf:1;
-+              uint32_t typ:2;
-+              uint32_t mspc:1;
-+      } s;
-+      struct cvmx_pci_cfg04_s cn30xx;
-+      struct cvmx_pci_cfg04_s cn31xx;
-+      struct cvmx_pci_cfg04_s cn38xx;
-+      struct cvmx_pci_cfg04_s cn38xxp2;
-+      struct cvmx_pci_cfg04_s cn50xx;
-+      struct cvmx_pci_cfg04_s cn58xx;
-+      struct cvmx_pci_cfg04_s cn58xxp1;
-+};
-+
-+union cvmx_pci_cfg05 {
-+      uint32_t u32;
-+      struct cvmx_pci_cfg05_s {
-+              uint32_t hbase:32;
-+      } s;