add fix from #1516

[openwrt-10.03/.git] / target / linux / brcm47xx-2.6 / files / drivers / ssb / driver_pci / pcicore.c

diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
index 9800ce66e2f24e2e293e55324c9849b5bbe555ee..d9aa22b351376c79d59176a567e037dc9eaa34eb 100644 (file)
--- a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
+++ b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_pci/pcicore.c
@@ -162,7 +162,6 @@ static int ssb_extpci_read_config(struct ssb_pcicore *pc,
                goto unmap;
        }
        
-       val = readl(mmio);
        val >>= (8 * (off & 3));
 
        switch (len) {
@@ -210,12 +209,10 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc,
 
        switch (len) {
        case 1:
-               val = readl(mmio);
                val &= ~(0xFF << (8 * (off & 3)));
                val |= *((const u8 *)buf) << (8 * (off & 3));
                break;
        case 2:
-               val = readl(mmio);
                val &= ~(0xFFFF << (8 * (off & 3)));
                val |= *((const u16 *)buf) << (8 * (off & 3));
                break;
@@ -223,7 +220,7 @@ static int ssb_extpci_write_config(struct ssb_pcicore *pc,
                val = *((const u32 *)buf);
                break;
        }
-       writel(*((const u32 *)buf), mmio);
+       writel(val, mmio);
 
        err = 0;
 unmap:
@@ -303,6 +300,8 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
        udelay(150);
        val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
        pcicore_write32(pc, SSB_PCICORE_CTL, val);
+       val = SSB_PCICORE_ARBCTL_INTERN;
+       pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 
        udelay(1);
 
        //TODO cardbus mode
@@ -329,6 +328,7 @@ static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
         * The following needs change, if we want to port hostmode
         * to non-MIPS platform. */
        set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
+       mdelay(300);
        register_pci_controller(&ssb_pcicore_controller);
 }