module_param(ag71xx_debug, int, 0);
MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
+static void ag71xx_dump_dma_regs(struct ag71xx *ag)
+{
+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_TX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
+
+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
+ ag->dev->name,
+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
+ ag71xx_rr(ag, AG71XX_REG_RX_DESC),
+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
+}
+
static void ag71xx_dump_regs(struct ag71xx *ag)
{
DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
}
+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
+{
+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
+ ag->dev->name, label, intr,
+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
+}
+
static void ag71xx_ring_free(struct ag71xx_ring *ring)
{
kfree(ring->buf);
u32 t;
t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
- | (((u32) mac[2]) << 8) | ((u32) mac[2]);
+ | (((u32) mac[2]) << 8) | ((u32) mac[3]);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
}
-#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
- | MAC_CFG1_STX)
+#define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX)
+#define AR71XX_FIFO_CFG5_INIT 0x0007ffef
+
+#define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
+ MAC_CFG1_SRX | MAC_CFG1_STX | \
+ MAC_CFG1_TFC | MAC_CFG1_RFC)
+#define AR91XX_FIFO_CFG5_INIT 0x0007efef
#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
+static void ag71xx_dma_reset(struct ag71xx *ag)
+{
+ int i;
+
+ ag71xx_dump_dma_regs(ag);
+
+ /* stop RX and TX */
+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
+
+ /* clear descriptor addresses */
+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
+
+ /* clear pending RX/TX interrupts */
+ for (i = 0; i < 256; i++) {
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
+ }
+
+ /* clear pending errors */
+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
+
+ if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
+ ag->dev->name);
+
+ if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
+ printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
+ ag->dev->name);
+
+ ag71xx_dump_dma_regs(ag);
+}
+
static void ag71xx_hw_init(struct ag71xx *ag)
{
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
ar71xx_device_start(pdata->reset_bit);
mdelay(100);
- ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
-
- /* TODO: set max packet size */
-
+ /* setup MAC configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
+ pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
+ /* setup max frame length */
+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
+ /* setup MII interface type */
ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
+ /* setup FIFO configuration registers */
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
+ pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
+ : AR71XX_FIFO_CFG5_INIT);
+
+ ag71xx_dma_reset(ag);
}
static void ag71xx_hw_start(struct ag71xx *ag)
static void ag71xx_hw_stop(struct ag71xx *ag)
{
- /* stop RX and TX */
- ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
- ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
-
/* disable all interrupts */
ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
+
+ ag71xx_dma_reset(ag);
}
static int ag71xx_open(struct net_device *dev)
desc = &ring->descs[i];
spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
spin_unlock_irqrestore(&ag->lock, flags);
if (!ag71xx_desc_empty(desc))
DBG("%s: processing TX ring\n", ag->dev->name);
#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
#endif
sent = 0;
#ifndef AG71XX_NAPI_TX
spin_lock_irqsave(&ag->lock, flags);
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
spin_unlock_irqrestore(&ag->lock, flags);
#endif
int done;
#ifdef AG71XX_NAPI_TX
- ar71xx_ddr_flush(pdata->flush_reg);
+ pdata->ddr_flush();
ag71xx_tx_packets(ag);
#endif
u32 status;
status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
+ ag71xx_dump_intr(ag, "raw", status);
status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
+ ag71xx_dump_intr(ag, "masked", status);
if (unlikely(!status))
return IRQ_NONE;
static void __exit ag71xx_module_exit(void)
{
platform_driver_unregister(&ag71xx_driver);
+ ag71xx_mdio_driver_exit();
}
module_init(ag71xx_module_init);
projects / openwrt-10.03 / .git / blobdiff