ar71xx: move PB42 specific PCI init code into a separate file

[openwrt-10.03/.git] / target / linux / ar71xx / files / arch / mips / ar71xx / mach-pb42.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
index 67efe8fd5c96de1c322d8b4a9dba4ffa62e82c5c..6e85155ccdaad2c7f2ffe4e8ac46ad48658bab30 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/mach-pb42.c
@@ -11,38 +11,36 @@
 
 #include <linux/init.h>
 #include <linux/bitops.h>
+#include <linux/input.h>
 #include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/flash.h>
 
 #include <asm/mips_machine.h>
 #include <asm/mach-ar71xx/ar71xx.h>
-#include <asm/mach-ar71xx/pci.h>
 
 #include "devices.h"
+#include "dev-m25p80.h"
+#include "dev-pb42-pci.h"
 
-static struct spi_board_info pb42_spi_info[] = {
-       {
-               .bus_num        = 0,
-               .chip_select    = 0,
-               .max_speed_hz   = 25000000,
-               .modalias       = "m25p80",
-       }
-};
+#define PB42_BUTTONS_POLL_INTERVAL     20
 
-static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
+#define PB42_GPIO_BTN_SW4      8
+#define PB42_GPIO_BTN_SW5      3
+
+static struct gpio_button pb42_gpio_buttons[] __initdata = {
        {
-               .slot   = 0,
-               .pin    = 1,
-               .irq    = AR71XX_PCI_IRQ_DEV0,
-       }, {
-               .slot   = 1,
-               .pin    = 1,
-               .irq    = AR71XX_PCI_IRQ_DEV1,
-       }, {
-               .slot   = 2,
-               .pin    = 1,
-               .irq    = AR71XX_PCI_IRQ_DEV2,
+               .desc           = "sw4",
+               .type           = EV_KEY,
+               .code           = BTN_0,
+               .threshold      = 5,
+               .gpio           = PB42_GPIO_BTN_SW4,
+               .active_low     = 1,
+       } , {
+               .desc           = "sw5",
+               .type           = EV_KEY,
+               .code           = BTN_1,
+               .threshold      = 5,
+               .gpio           = PB42_GPIO_BTN_SW5,
+               .active_low     = 1,
        }
 };
 
@@ -52,8 +50,7 @@ static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
 
 static void __init pb42_init(void)
 {
-       ar71xx_add_device_spi(NULL, pb42_spi_info,
-                               ARRAY_SIZE(pb42_spi_info));
+       ar71xx_add_device_m25p80(NULL);
 
        ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
 
@@ -68,7 +65,11 @@ static void __init pb42_init(void)
        ar71xx_add_device_eth(0);
        ar71xx_add_device_eth(1);
 
-       ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
+       ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
+                                      ARRAY_SIZE(pb42_gpio_buttons),
+                                      pb42_gpio_buttons);
+
+       pb42_pci_init();
 }
 
 MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);