/*
* Atheros AR71xx SoC platform devices
*
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* Parts of this file are based on Atheros' 2.6.15 BSP
#include <linux/ath9k_platform.h>
#include <asm/mach-ar71xx/ar71xx.h>
-#include <asm/mach-ar71xx/platform.h>
+
+#include "devices.h"
static u8 ar71xx_mac_base[ETH_ALEN] __initdata;
}
}
-#ifndef CONFIG_AR71XX_EARLY_SERIAL
static struct resource ar71xx_uart_resources[] = {
{
.start = AR71XX_UART_BASE,
ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
platform_device_register(&ar71xx_uart_device);
}
-#endif /* CONFIG_AR71XX_EARLY_SERIAL */
static struct resource ar71xx_mdio_resources[] = {
{
.name = "mdio_base",
.flags = IORESOURCE_MEM,
- .start = AR71XX_GE0_BASE + 0x20,
- .end = AR71XX_GE0_BASE + 0x38 - 1,
+ .start = AR71XX_GE0_BASE,
+ .end = AR71XX_GE0_BASE + 0x200 - 1,
}
};
iounmap(base);
}
-static void ar71xx_set_pll_ge0(u32 val)
+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
+
+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
+{
+ struct ar71xx_eth_pll_data *pll_data;
+ u32 pll_val;
+
+ switch (mac) {
+ case 0:
+ pll_data = &ar71xx_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ar71xx_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (speed) {
+ case SPEED_10:
+ pll_val = pll_data->pll_10;
+ break;
+ case SPEED_100:
+ pll_val = pll_data->pll_100;
+ break;
+ case SPEED_1000:
+ pll_val = pll_data->pll_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ return pll_val;
+}
+
+static void ar71xx_set_pll_ge0(int speed)
{
+ u32 val = ar71xx_get_eth_pll(0, speed);
+
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
val, AR71XX_ETH0_PLL_SHIFT);
}
-static void ar71xx_set_pll_ge1(u32 val)
+static void ar71xx_set_pll_ge1(int speed)
{
+ u32 val = ar71xx_get_eth_pll(1, speed);
+
ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
val, AR71XX_ETH1_PLL_SHIFT);
}
-static void ar91xx_set_pll_ge0(u32 val)
+static void ar724x_set_pll_ge0(int speed)
+{
+ /* TODO */
+}
+
+static void ar724x_set_pll_ge1(int speed)
+{
+ /* TODO */
+}
+
+static void ar91xx_set_pll_ge0(int speed)
{
+ u32 val = ar71xx_get_eth_pll(0, speed);
+
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
val, AR91XX_ETH0_PLL_SHIFT);
}
-static void ar91xx_set_pll_ge1(u32 val)
+static void ar91xx_set_pll_ge1(int speed)
{
+ u32 val = ar71xx_get_eth_pll(1, speed);
+
ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
val, AR91XX_ETH1_PLL_SHIFT);
}
ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
}
+static void ar724x_ddr_flush_ge0(void)
+{
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar724x_ddr_flush_ge1(void)
+{
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
+}
+
static void ar91xx_ddr_flush_ge0(void)
{
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE0_BASE,
- .end = AR71XX_GE0_BASE + 0x20 - 1,
- }, {
- .name = "mac_base2",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_GE0_BASE + 0x38,
.end = AR71XX_GE0_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
.name = "mac_base",
.flags = IORESOURCE_MEM,
.start = AR71XX_GE1_BASE,
- .end = AR71XX_GE1_BASE + 0x20 - 1,
- }, {
- .name = "mac_base2",
- .flags = IORESOURCE_MEM,
- .start = AR71XX_GE1_BASE + 0x38,
.end = AR71XX_GE1_BASE + 0x200 - 1,
}, {
.name = "mii_ctrl",
},
};
+#define AR71XX_PLL_VAL_1000 0x00110000
+#define AR71XX_PLL_VAL_100 0x00001099
+#define AR71XX_PLL_VAL_10 0x00991099
+
+#define AR724X_PLL_VAL_1000 0x00110000
+#define AR724X_PLL_VAL_100 0x00001099
+#define AR724X_PLL_VAL_10 0x00991099
+
+#define AR91XX_PLL_VAL_1000 0x1a000000
+#define AR91XX_PLL_VAL_100 0x13000a44
+#define AR91XX_PLL_VAL_10 0x00441099
+
+static void __init ar71xx_init_eth_pll_data(unsigned int id)
+{
+ struct ar71xx_eth_pll_data *pll_data;
+ u32 pll_10, pll_100, pll_1000;
+
+ switch (id) {
+ case 0:
+ pll_data = &ar71xx_eth0_pll_data;
+ break;
+ case 1:
+ pll_data = &ar71xx_eth1_pll_data;
+ break;
+ default:
+ BUG();
+ }
+
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7130:
+ case AR71XX_SOC_AR7141:
+ case AR71XX_SOC_AR7161:
+ pll_10 = AR71XX_PLL_VAL_10;
+ pll_100 = AR71XX_PLL_VAL_100;
+ pll_1000 = AR71XX_PLL_VAL_1000;
+ break;
+
+ case AR71XX_SOC_AR7240:
+ pll_10 = AR724X_PLL_VAL_10;
+ pll_100 = AR724X_PLL_VAL_100;
+ pll_1000 = AR724X_PLL_VAL_1000;
+ break;
+
+ case AR71XX_SOC_AR9130:
+ case AR71XX_SOC_AR9132:
+ pll_10 = AR91XX_PLL_VAL_10;
+ pll_100 = AR91XX_PLL_VAL_100;
+ pll_1000 = AR91XX_PLL_VAL_1000;
+ break;
+ default:
+ BUG();
+ }
+
+ if (!pll_data->pll_10)
+ pll_data->pll_10 = pll_10;
+
+ if (!pll_data->pll_100)
+ pll_data->pll_100 = pll_100;
+
+ if (!pll_data->pll_1000)
+ pll_data->pll_1000 = pll_1000;
+}
+
static int ar71xx_eth_instance __initdata;
void __init ar71xx_add_device_eth(unsigned int id)
{
struct platform_device *pdev;
struct ag71xx_platform_data *pdata;
+ ar71xx_init_eth_pll_data(id);
+
switch (id) {
case 0:
switch (ar71xx_eth0_data.phy_if_mode) {
pdata->has_gbit = 1;
break;
+ case AR71XX_SOC_AR7240:
+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
+ : ar724x_ddr_flush_ge0;
+ pdata->set_pll = id ? ar724x_set_pll_ge1
+ : ar724x_set_pll_ge0;
+ pdata->is_ar724x = 1;
+ break;
+
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;
platform_device_register(&ar91xx_wmac_device);
}
+
+static struct platform_device ar71xx_dsa_switch_device = {
+ .name = "dsa",
+ .id = 0,
+};
+
+void __init ar71xx_add_device_dsa(unsigned int id,
+ struct dsa_platform_data *d)
+{
+ switch (id) {
+ case 0:
+ d->netdev = &ar71xx_eth0_device.dev;
+ break;
+ case 1:
+ d->netdev = &ar71xx_eth1_device.dev;
+ break;
+ default:
+ printk(KERN_ERR
+ "ar71xx: invalid ethernet id %d for DSA switch\n",
+ id);
+ return;
+ }
+ d->mii_bus = &ar71xx_mdio_device.dev;
+ ar71xx_dsa_switch_device.dev.platform_data = d;
+
+ platform_device_register(&ar71xx_dsa_switch_device);
+}
projects / openwrt-10.03 / .git / blobdiff