ar71xx: backport ar7241/ar7242 fixes from trunk

[openwrt-10.03/.git] / target / linux / ar71xx / files / arch / mips / ar71xx / dev-ap91-pci.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
index e81a01aba764ce65c0b7f26483379e581230c1f6..abcb6b67edaab42b5d90dd248f8c568f3ebb79cc 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/dev-ap91-pci.c
@@ -17,7 +17,9 @@
 
 #include "dev-ap91-pci.h"
 
-static struct ath9k_platform_data ap91_wmac_data;
+static struct ath9k_platform_data ap91_wmac_data = {
+       .led_pin = -1,
+};
 static char ap91_wmac_mac[6];
 static int ap91_pci_fixup_enabled;
 
@@ -45,6 +47,7 @@ static void ap91_pci_fixup(struct pci_dev *dev)
        void __iomem *mem;
        u16 *cal_data;
        u16 cmd;
+       u32 bar0;
        u32 val;
 
        if (!ap91_pci_fixup_enabled)
@@ -67,7 +70,22 @@ static void ap91_pci_fixup(struct pci_dev *dev)
        }
 
        /* Setup the PCI device to allow access to the internal registers */
-       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
+       pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
+
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7240:
+               pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff);
+               break;
+
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff);
+               break;
+
+       default:
+               break;
+       }
+
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
        pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -92,10 +110,27 @@ static void ap91_pci_fixup(struct pci_dev *dev)
        dev->revision = val & 0xff;
        dev->class = val >> 8; /* upper 3 bytes */
 
+       pci_read_config_word(dev, PCI_COMMAND, &cmd);
+       cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+       pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
+
        iounmap(mem);
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup);
 
+__init void ap91_pci_setup_wmac_led_pin(int pin)
+{
+       ap91_wmac_data.led_pin = pin;
+}
+
+__init void ap91_pci_setup_wmac_gpio(u32 mask, u32 val)
+{
+       ap91_wmac_data.gpio_mask = mask;
+       ap91_wmac_data.gpio_val = val;
+}
+
 void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr)
 {
        if (cal_data)