[backfire] target: remove empty "ifxmips" dir
[openwrt-10.03/.git] / target / linux / kirkwood / patches / 003-gating.patch
1 From: Rabeeh Khoury <rabeeh@marvell.com>
2 Date: Sun, 22 Mar 2009 15:30:32 +0000 (+0200)
3 Subject: [ARM] Kirkwood: peripherals clock gating for power management
4 X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=c0c3df02efed0e5dea9aa4d8313e06e1f68f2cb4;hp=039b97666e1335eac517c7d35a0fa1143af689f0
5
6 [ARM] Kirkwood: peripherals clock gating for power management
7
8 1. Enabling clock gating of unused peripherals
9 2. PLL and PHY of the units are also disabled (when possible.
10
11 Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
12
13 [ This needs to be revisited to make power handling dynamic and per device.  -- Nico ]
14
15 ---
16
17 --- a/arch/arm/mach-kirkwood/common.c
18 +++ b/arch/arm/mach-kirkwood/common.c
19 @@ -786,6 +786,38 @@ static void __init kirkwood_l2_init(void
20  #endif
21  }
22  
23 +void __init kirkwood_clock_gate(u32 reg)
24 +{
25 +       printk(KERN_INFO "Kirkwood: Gating clock using mask 0x%x\n", reg);
26 +       /* First make sure that the units are accessible */
27 +       writel(readl(CLOCK_GATING_CTRL) | reg, CLOCK_GATING_CTRL);
28 +       /* For SATA first shutdown the phy */
29 +       if (reg & CGC_SATA0) {
30 +               /* Disable PLL and IVREF */
31 +               writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
32 +               /* Disable PHY */
33 +               writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
34 +       }
35 +       if (reg & CGC_SATA1) {
36 +               /* Disable PLL and IVREF */
37 +               writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
38 +               /* Disable PHY */
39 +               writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
40 +       }
41 +       /* For PCI-E first shutdown the phy */
42 +       if (reg & CGC_PEX0) {
43 +               writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
44 +               while (1) {
45 +                       if (readl(PCIE_STATUS) & 0x1)
46 +                               break;
47 +               }
48 +               writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
49 +       }
50 +       /* Now gate clock the required units */
51 +       writel(readl(CLOCK_GATING_CTRL) & ~reg, CLOCK_GATING_CTRL);
52 +       return;
53 +}
54 +
55  void __init kirkwood_init(void)
56  {
57         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
58 --- a/arch/arm/mach-kirkwood/common.h
59 +++ b/arch/arm/mach-kirkwood/common.h
60 @@ -22,6 +22,7 @@ struct mvsdio_platform_data;
61  void kirkwood_map_io(void);
62  void kirkwood_init(void);
63  void kirkwood_init_irq(void);
64 +void __init kirkwood_clock_gate(u32 reg);
65  
66  extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
67  void kirkwood_setup_cpu_mbus(void);
68 --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
69 +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
70 @@ -39,4 +39,20 @@
71  #define L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
72  #define L2_WRITETHROUGH                0x00000010
73  
74 +#define CLOCK_GATING_CTRL      (BRIDGE_VIRT_BASE | 0x11c)
75 +#define CGC_GE0                        0x1
76 +#define CGC_PEX0               0x4
77 +#define CGC_USB0               0x8
78 +#define CGC_SDIO               0x10
79 +#define CGC_TSU                        0x20
80 +#define CGC_NAND_SPI           0x80
81 +#define CGC_XOR0               0x100
82 +#define CGC_AUDIO              0x200
83 +#define CGC_SATA0              0x4000
84 +#define CGC_SATA1              0x8000
85 +#define CGC_XOR1               0x10000
86 +#define CGC_CRYPTO             0x20000
87 +#define CGC_GE1                        0x80000
88 +#define CGC_TDM                        0x100000
89 +
90  #endif
91 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
92 +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
93 @@ -64,6 +64,8 @@
94  #define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
95  
96  #define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
97 +#define PCIE_LINK_CTRL         (PCIE_VIRT_BASE | 0x70)
98 +#define PCIE_STATUS            (PCIE_VIRT_BASE | 0x1a04)
99  
100  #define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
101  
102 @@ -80,6 +82,11 @@
103  #define GE01_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
104  
105  #define SATA_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
106 +#define SATA_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
107 +#define SATA0_IF_CTRL          (SATA_VIRT_BASE | 0x2050)
108 +#define SATA0_PHY_MODE_2       (SATA_VIRT_BASE | 0x2330)
109 +#define SATA1_IF_CTRL          (SATA_VIRT_BASE | 0x4050)
110 +#define SATA1_PHY_MODE_2       (SATA_VIRT_BASE | 0x4330)
111  
112  #define SDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
113  
114 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
115 +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
116 @@ -19,6 +19,7 @@
117  #include <asm/mach-types.h>
118  #include <asm/mach/arch.h>
119  #include <mach/kirkwood.h>
120 +#include <mach/bridge-regs.h>
121  #include <plat/mvsdio.h>
122  #include <plat/orion_nand.h>
123  #include "common.h"
124 @@ -122,6 +123,8 @@ static void __init sheevaplug_init(void)
125  
126         platform_device_register(&sheevaplug_nand_flash);
127         platform_device_register(&sheevaplug_leds);
128 +       kirkwood_clock_gate(CGC_PEX0 | CGC_TSU | CGC_AUDIO | CGC_SATA0 |\
129 +                               CGC_SATA1 | CGC_CRYPTO | CGC_GE1 | CGC_TDM);
130  }
131  
132  MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")