ar71xx: add dummy debugfs support for the ag71xx driver
[openwrt-10.03/.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2  *  Atheros AR71xx built-in ethernet mac driver
3  *
4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6  *
7  *  Based on Atheros' AG7100 driver
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License version 2 as published
11  *  by the Free Software Foundation.
12  */
13
14 #include <linux/cache.h>
15 #include "ag71xx.h"
16
17 #define AG71XX_DEFAULT_MSG_ENABLE       \
18         ( NETIF_MSG_DRV                 \
19         | NETIF_MSG_PROBE               \
20         | NETIF_MSG_LINK                \
21         | NETIF_MSG_TIMER               \
22         | NETIF_MSG_IFDOWN              \
23         | NETIF_MSG_IFUP                \
24         | NETIF_MSG_RX_ERR              \
25         | NETIF_MSG_TX_ERR )
26
27 static int ag71xx_msg_level = -1;
28
29 module_param_named(msg_level, ag71xx_msg_level, int, 0);
30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31
32 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 {
34         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35                 ag->dev->name,
36                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
37                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
38                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39
40         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41                 ag->dev->name,
42                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
43                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
44                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
45 }
46
47 static void ag71xx_dump_regs(struct ag71xx *ag)
48 {
49         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50                 ag->dev->name,
51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
52                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
53                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
54                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
55                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
56         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57                 ag->dev->name,
58                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
60                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
61         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62                 ag->dev->name,
63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
65                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
66         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67                 ag->dev->name,
68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
70                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
71 }
72
73 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 {
75         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
76                 ag->dev->name, label, intr,
77                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
78                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
79                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
80                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
81                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
82                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
83 }
84
85 static void ag71xx_ring_free(struct ag71xx_ring *ring)
86 {
87         kfree(ring->buf);
88
89         if (ring->descs_cpu)
90                 dma_free_coherent(NULL, ring->size * ring->desc_size,
91                                   ring->descs_cpu, ring->descs_dma);
92 }
93
94 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
95 {
96         int err;
97         int i;
98
99         ring->desc_size = sizeof(struct ag71xx_desc);
100         if (ring->desc_size % cache_line_size()) {
101                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
102                         ring, ring->desc_size,
103                         roundup(ring->desc_size, cache_line_size()));
104                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
105         }
106
107         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
108                                              &ring->descs_dma, GFP_ATOMIC);
109         if (!ring->descs_cpu) {
110                 err = -ENOMEM;
111                 goto err;
112         }
113
114         ring->size = size;
115
116         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
117         if (!ring->buf) {
118                 err = -ENOMEM;
119                 goto err;
120         }
121
122         for (i = 0; i < size; i++) {
123                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
124                 DBG("ag71xx: ring %p, desc %d at %p\n",
125                         ring, i, ring->buf[i].desc);
126         }
127
128         return 0;
129
130  err:
131         return err;
132 }
133
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 {
136         struct ag71xx_ring *ring = &ag->tx_ring;
137         struct net_device *dev = ag->dev;
138
139         while (ring->curr != ring->dirty) {
140                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
141
142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143                         ring->buf[i].desc->ctrl = 0;
144                         dev->stats.tx_errors++;
145                 }
146
147                 if (ring->buf[i].skb)
148                         dev_kfree_skb_any(ring->buf[i].skb);
149
150                 ring->buf[i].skb = NULL;
151
152                 ring->dirty++;
153         }
154
155         /* flush descriptors */
156         wmb();
157
158 }
159
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 {
162         struct ag71xx_ring *ring = &ag->tx_ring;
163         int i;
164
165         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
168
169                 ring->buf[i].desc->ctrl = DESC_EMPTY;
170                 ring->buf[i].skb = NULL;
171         }
172
173         /* flush descriptors */
174         wmb();
175
176         ring->curr = 0;
177         ring->dirty = 0;
178 }
179
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
181 {
182         struct ag71xx_ring *ring = &ag->rx_ring;
183         int i;
184
185         if (!ring->buf)
186                 return;
187
188         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189                 if (ring->buf[i].skb)
190                         kfree_skb(ring->buf[i].skb);
191
192 }
193
194 static int ag71xx_ring_rx_init(struct ag71xx *ag)
195 {
196         struct ag71xx_ring *ring = &ag->rx_ring;
197         unsigned int i;
198         int ret;
199
200         ret = 0;
201         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
202                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
203                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
204
205                 DBG("ag71xx: RX desc at %p, next is %08x\n",
206                         ring->buf[i].desc,
207                         ring->buf[i].desc->next);
208         }
209
210         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
211                 struct sk_buff *skb;
212
213                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
214                 if (!skb) {
215                         ret = -ENOMEM;
216                         break;
217                 }
218
219                 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
220                                 DMA_FROM_DEVICE);
221
222                 skb->dev = ag->dev;
223                 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
224
225                 ring->buf[i].skb = skb;
226                 ring->buf[i].desc->data = virt_to_phys(skb->data);
227                 ring->buf[i].desc->ctrl = DESC_EMPTY;
228         }
229
230         /* flush descriptors */
231         wmb();
232
233         ring->curr = 0;
234         ring->dirty = 0;
235
236         return ret;
237 }
238
239 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
240 {
241         struct ag71xx_ring *ring = &ag->rx_ring;
242         unsigned int count;
243
244         count = 0;
245         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
246                 unsigned int i;
247
248                 i = ring->dirty % AG71XX_RX_RING_SIZE;
249
250                 if (ring->buf[i].skb == NULL) {
251                         struct sk_buff *skb;
252
253                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
254                         if (skb == NULL)
255                                 break;
256
257                         dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
258                                         DMA_FROM_DEVICE);
259
260                         skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
261                         skb->dev = ag->dev;
262
263                         ring->buf[i].skb = skb;
264                         ring->buf[i].desc->data = virt_to_phys(skb->data);
265                 }
266
267                 ring->buf[i].desc->ctrl = DESC_EMPTY;
268                 count++;
269         }
270
271         /* flush descriptors */
272         wmb();
273
274         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
275
276         return count;
277 }
278
279 static int ag71xx_rings_init(struct ag71xx *ag)
280 {
281         int ret;
282
283         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
284         if (ret)
285                 return ret;
286
287         ag71xx_ring_tx_init(ag);
288
289         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
290         if (ret)
291                 return ret;
292
293         ret = ag71xx_ring_rx_init(ag);
294         return ret;
295 }
296
297 static void ag71xx_rings_cleanup(struct ag71xx *ag)
298 {
299         ag71xx_ring_rx_clean(ag);
300         ag71xx_ring_free(&ag->rx_ring);
301
302         ag71xx_ring_tx_clean(ag);
303         ag71xx_ring_free(&ag->tx_ring);
304 }
305
306 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
307 {
308         u32 t;
309
310         t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
311           | (((u32) mac[2]) << 8) | ((u32) mac[3]);
312
313         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
314
315         t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
316         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
317 }
318
319 static void ag71xx_dma_reset(struct ag71xx *ag)
320 {
321         u32 val;
322         int i;
323
324         ag71xx_dump_dma_regs(ag);
325
326         /* stop RX and TX */
327         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
328         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
329
330         /* clear descriptor addresses */
331         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
332         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
333
334         /* clear pending RX/TX interrupts */
335         for (i = 0; i < 256; i++) {
336                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
337                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
338         }
339
340         /* clear pending errors */
341         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
342         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
343
344         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
345         if (val)
346                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
347                         ag->dev->name, val);
348
349         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
350
351         /* mask out reserved bits */
352         val &= ~0xff000000;
353
354         if (val)
355                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
356                         ag->dev->name, val);
357
358         ag71xx_dump_dma_regs(ag);
359 }
360
361 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
362                          MAC_CFG1_SRX | MAC_CFG1_STX)
363
364 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
365
366 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
367                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
368                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
369                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
370                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
371                          FIFO_CFG4_VT)
372
373 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
374                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
375                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
376                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
377                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
378                          FIFO_CFG5_17 | FIFO_CFG5_SF)
379
380 static void ag71xx_hw_init(struct ag71xx *ag)
381 {
382         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
383
384         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
385         udelay(20);
386
387         ar71xx_device_stop(pdata->reset_bit);
388         mdelay(100);
389         ar71xx_device_start(pdata->reset_bit);
390         mdelay(100);
391
392         /* setup MAC configuration registers */
393         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
394         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
395                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
396
397         /* setup max frame length */
398         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
399
400         /* setup MII interface type */
401         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
402
403         /* setup FIFO configuration registers */
404         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
405         if (pdata->is_ar724x) {
406                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
407                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
408         } else {
409                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
410                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
411         }
412         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
413         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
414
415         ag71xx_dma_reset(ag);
416 }
417
418 static void ag71xx_hw_start(struct ag71xx *ag)
419 {
420         /* start RX engine */
421         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
422
423         /* enable interrupts */
424         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
425 }
426
427 static void ag71xx_hw_stop(struct ag71xx *ag)
428 {
429         /* disable all interrupts */
430         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
431
432         ag71xx_dma_reset(ag);
433 }
434
435 static int ag71xx_open(struct net_device *dev)
436 {
437         struct ag71xx *ag = netdev_priv(dev);
438         int ret;
439
440         ret = ag71xx_rings_init(ag);
441         if (ret)
442                 goto err;
443
444         napi_enable(&ag->napi);
445
446         netif_carrier_off(dev);
447         ag71xx_phy_start(ag);
448
449         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
450         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
451
452         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
453
454         ag71xx_hw_start(ag);
455
456         netif_start_queue(dev);
457
458         return 0;
459
460  err:
461         ag71xx_rings_cleanup(ag);
462         return ret;
463 }
464
465 static int ag71xx_stop(struct net_device *dev)
466 {
467         struct ag71xx *ag = netdev_priv(dev);
468         unsigned long flags;
469
470         spin_lock_irqsave(&ag->lock, flags);
471
472         netif_stop_queue(dev);
473
474         ag71xx_hw_stop(ag);
475
476         netif_carrier_off(dev);
477         ag71xx_phy_stop(ag);
478
479         napi_disable(&ag->napi);
480         del_timer_sync(&ag->oom_timer);
481
482         spin_unlock_irqrestore(&ag->lock, flags);
483
484         ag71xx_rings_cleanup(ag);
485
486         return 0;
487 }
488
489 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
490 {
491         struct ag71xx *ag = netdev_priv(dev);
492         struct ag71xx_ring *ring = &ag->tx_ring;
493         struct ag71xx_desc *desc;
494         int i;
495
496         i = ring->curr % AG71XX_TX_RING_SIZE;
497         desc = ring->buf[i].desc;
498
499         if (!ag71xx_desc_empty(desc))
500                 goto err_drop;
501
502         ag71xx_add_ar8216_header(ag, skb);
503
504         if (skb->len <= 0) {
505                 DBG("%s: packet len is too small\n", ag->dev->name);
506                 goto err_drop;
507         }
508
509         dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
510
511         ring->buf[i].skb = skb;
512
513         /* setup descriptor fields */
514         desc->data = virt_to_phys(skb->data);
515         desc->ctrl = (skb->len & DESC_PKTLEN_M);
516
517         /* flush descriptor */
518         wmb();
519
520         ring->curr++;
521         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
522                 DBG("%s: tx queue full\n", ag->dev->name);
523                 netif_stop_queue(dev);
524         }
525
526         DBG("%s: packet injected into TX queue\n", ag->dev->name);
527
528         /* enable TX engine */
529         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
530
531         dev->trans_start = jiffies;
532
533         return 0;
534
535  err_drop:
536         dev->stats.tx_dropped++;
537
538         dev_kfree_skb(skb);
539         return 0;
540 }
541
542 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
543 {
544         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
545         struct ag71xx *ag = netdev_priv(dev);
546         int ret;
547
548         switch (cmd) {
549         case SIOCETHTOOL:
550                 if (ag->phy_dev == NULL)
551                         break;
552
553                 spin_lock_irq(&ag->lock);
554                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
555                 spin_unlock_irq(&ag->lock);
556                 return ret;
557
558         case SIOCSIFHWADDR:
559                 if (copy_from_user
560                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
561                         return -EFAULT;
562                 return 0;
563
564         case SIOCGIFHWADDR:
565                 if (copy_to_user
566                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
567                         return -EFAULT;
568                 return 0;
569
570         case SIOCGMIIPHY:
571         case SIOCGMIIREG:
572         case SIOCSMIIREG:
573                 if (ag->phy_dev == NULL)
574                         break;
575
576                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
577
578         default:
579                 break;
580         }
581
582         return -EOPNOTSUPP;
583 }
584
585 static void ag71xx_oom_timer_handler(unsigned long data)
586 {
587         struct net_device *dev = (struct net_device *) data;
588         struct ag71xx *ag = netdev_priv(dev);
589
590         napi_schedule(&ag->napi);
591 }
592
593 static void ag71xx_tx_timeout(struct net_device *dev)
594 {
595         struct ag71xx *ag = netdev_priv(dev);
596
597         if (netif_msg_tx_err(ag))
598                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
599
600         schedule_work(&ag->restart_work);
601 }
602
603 static void ag71xx_restart_work_func(struct work_struct *work)
604 {
605         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
606
607         ag71xx_stop(ag->dev);
608         ag71xx_open(ag->dev);
609 }
610
611 static void ag71xx_tx_packets(struct ag71xx *ag)
612 {
613         struct ag71xx_ring *ring = &ag->tx_ring;
614         unsigned int sent;
615
616         DBG("%s: processing TX ring\n", ag->dev->name);
617
618         sent = 0;
619         while (ring->dirty != ring->curr) {
620                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
621                 struct ag71xx_desc *desc = ring->buf[i].desc;
622                 struct sk_buff *skb = ring->buf[i].skb;
623
624                 if (!ag71xx_desc_empty(desc))
625                         break;
626
627                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
628
629                 ag->dev->stats.tx_bytes += skb->len;
630                 ag->dev->stats.tx_packets++;
631
632                 dev_kfree_skb_any(skb);
633                 ring->buf[i].skb = NULL;
634
635                 ring->dirty++;
636                 sent++;
637         }
638
639         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
640
641         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
642                 netif_wake_queue(ag->dev);
643
644 }
645
646 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
647 {
648         struct net_device *dev = ag->dev;
649         struct ag71xx_ring *ring = &ag->rx_ring;
650         int done = 0;
651
652         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
653                         dev->name, limit, ring->curr, ring->dirty);
654
655         while (done < limit) {
656                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
657                 struct ag71xx_desc *desc = ring->buf[i].desc;
658                 struct sk_buff *skb;
659                 int pktlen;
660
661                 if (ag71xx_desc_empty(desc))
662                         break;
663
664                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
665                         ag71xx_assert(0);
666                         break;
667                 }
668
669                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
670
671                 skb = ring->buf[i].skb;
672                 pktlen = ag71xx_desc_pktlen(desc);
673                 pktlen -= ETH_FCS_LEN;
674
675                 skb_put(skb, pktlen);
676
677                 skb->dev = dev;
678                 skb->ip_summed = CHECKSUM_NONE;
679
680                 dev->last_rx = jiffies;
681                 dev->stats.rx_packets++;
682                 dev->stats.rx_bytes += pktlen;
683
684                 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
685                         dev->stats.rx_dropped++;
686                         kfree_skb(skb);
687                 } else {
688                         skb->protocol = eth_type_trans(skb, dev);
689                         netif_receive_skb(skb);
690                 }
691
692                 ring->buf[i].skb = NULL;
693                 done++;
694
695                 ring->curr++;
696         }
697
698         ag71xx_ring_rx_refill(ag);
699
700         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
701                 dev->name, ring->curr, ring->dirty, done);
702
703         return done;
704 }
705
706 static int ag71xx_poll(struct napi_struct *napi, int limit)
707 {
708         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
709         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
710         struct net_device *dev = ag->dev;
711         struct ag71xx_ring *rx_ring;
712         unsigned long flags;
713         u32 status;
714         int done;
715
716         pdata->ddr_flush();
717         ag71xx_tx_packets(ag);
718
719         DBG("%s: processing RX ring\n", dev->name);
720         done = ag71xx_rx_packets(ag, limit);
721
722         rx_ring = &ag->rx_ring;
723         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
724                 goto oom;
725
726         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
727         if (unlikely(status & RX_STATUS_OF)) {
728                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
729                 dev->stats.rx_fifo_errors++;
730
731                 /* restart RX */
732                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
733         }
734
735         if (done < limit) {
736                 if (status & RX_STATUS_PR)
737                         goto more;
738
739                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
740                 if (status & TX_STATUS_PS)
741                         goto more;
742
743                 DBG("%s: disable polling mode, done=%d, limit=%d\n",
744                         dev->name, done, limit);
745
746                 napi_complete(napi);
747
748                 /* enable interrupts */
749                 spin_lock_irqsave(&ag->lock, flags);
750                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
751                 spin_unlock_irqrestore(&ag->lock, flags);
752                 return done;
753         }
754
755  more:
756         DBG("%s: stay in polling mode, done=%d, limit=%d\n",
757                         dev->name, done, limit);
758         return done;
759
760  oom:
761         if (netif_msg_rx_err(ag))
762                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
763
764         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
765         napi_complete(napi);
766         return 0;
767 }
768
769 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
770 {
771         struct net_device *dev = dev_id;
772         struct ag71xx *ag = netdev_priv(dev);
773         u32 status;
774
775         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
776         ag71xx_dump_intr(ag, "raw", status);
777
778         if (unlikely(!status))
779                 return IRQ_NONE;
780
781         if (unlikely(status & AG71XX_INT_ERR)) {
782                 if (status & AG71XX_INT_TX_BE) {
783                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
784                         dev_err(&dev->dev, "TX BUS error\n");
785                 }
786                 if (status & AG71XX_INT_RX_BE) {
787                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
788                         dev_err(&dev->dev, "RX BUS error\n");
789                 }
790         }
791
792         if (likely(status & AG71XX_INT_POLL)) {
793                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
794                 DBG("%s: enable polling mode\n", dev->name);
795                 napi_schedule(&ag->napi);
796         }
797
798         return IRQ_HANDLED;
799 }
800
801 static void ag71xx_set_multicast_list(struct net_device *dev)
802 {
803         /* TODO */
804 }
805
806 static const struct net_device_ops ag71xx_netdev_ops = {
807         .ndo_open               = ag71xx_open,
808         .ndo_stop               = ag71xx_stop,
809         .ndo_start_xmit         = ag71xx_hard_start_xmit,
810         .ndo_set_multicast_list = ag71xx_set_multicast_list,
811         .ndo_do_ioctl           = ag71xx_do_ioctl,
812         .ndo_tx_timeout         = ag71xx_tx_timeout,
813         .ndo_change_mtu         = eth_change_mtu,
814         .ndo_set_mac_address    = eth_mac_addr,
815         .ndo_validate_addr      = eth_validate_addr,
816 };
817
818 static int __init ag71xx_probe(struct platform_device *pdev)
819 {
820         struct net_device *dev;
821         struct resource *res;
822         struct ag71xx *ag;
823         struct ag71xx_platform_data *pdata;
824         int err;
825
826         pdata = pdev->dev.platform_data;
827         if (!pdata) {
828                 dev_err(&pdev->dev, "no platform data specified\n");
829                 err = -ENXIO;
830                 goto err_out;
831         }
832
833         if (pdata->mii_bus_dev == NULL) {
834                 dev_err(&pdev->dev, "no MII bus device specified\n");
835                 err = -EINVAL;
836                 goto err_out;
837         }
838
839         dev = alloc_etherdev(sizeof(*ag));
840         if (!dev) {
841                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
842                 err = -ENOMEM;
843                 goto err_out;
844         }
845
846         SET_NETDEV_DEV(dev, &pdev->dev);
847
848         ag = netdev_priv(dev);
849         ag->pdev = pdev;
850         ag->dev = dev;
851         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
852                                         AG71XX_DEFAULT_MSG_ENABLE);
853         spin_lock_init(&ag->lock);
854
855         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
856         if (!res) {
857                 dev_err(&pdev->dev, "no mac_base resource found\n");
858                 err = -ENXIO;
859                 goto err_out;
860         }
861
862         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
863         if (!ag->mac_base) {
864                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
865                 err = -ENOMEM;
866                 goto err_free_dev;
867         }
868
869         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
870         if (!res) {
871                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
872                 err = -ENXIO;
873                 goto err_unmap_base;
874         }
875
876         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
877         if (!ag->mii_ctrl) {
878                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
879                 err = -ENOMEM;
880                 goto err_unmap_base;
881         }
882
883         dev->irq = platform_get_irq(pdev, 0);
884         err = request_irq(dev->irq, ag71xx_interrupt,
885                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
886                           dev->name, dev);
887         if (err) {
888                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
889                 goto err_unmap_mii_ctrl;
890         }
891
892         dev->base_addr = (unsigned long)ag->mac_base;
893         dev->netdev_ops = &ag71xx_netdev_ops;
894         dev->ethtool_ops = &ag71xx_ethtool_ops;
895
896         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
897
898         init_timer(&ag->oom_timer);
899         ag->oom_timer.data = (unsigned long) dev;
900         ag->oom_timer.function = ag71xx_oom_timer_handler;
901
902         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
903
904         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
905
906         err = register_netdev(dev);
907         if (err) {
908                 dev_err(&pdev->dev, "unable to register net device\n");
909                 goto err_free_irq;
910         }
911
912         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
913                dev->name, dev->base_addr, dev->irq);
914
915         ag71xx_dump_regs(ag);
916
917         ag71xx_hw_init(ag);
918
919         ag71xx_dump_regs(ag);
920
921         err = ag71xx_phy_connect(ag);
922         if (err)
923                 goto err_unregister_netdev;
924
925         err = ag71xx_debugfs_init(ag);
926         if (err)
927                 goto err_phy_disconnect;
928
929         platform_set_drvdata(pdev, dev);
930
931         return 0;
932
933  err_phy_disconnect:
934         ag71xx_phy_disconnect(ag);
935  err_unregister_netdev:
936         unregister_netdev(dev);
937  err_free_irq:
938         free_irq(dev->irq, dev);
939  err_unmap_mii_ctrl:
940         iounmap(ag->mii_ctrl);
941  err_unmap_base:
942         iounmap(ag->mac_base);
943  err_free_dev:
944         kfree(dev);
945  err_out:
946         platform_set_drvdata(pdev, NULL);
947         return err;
948 }
949
950 static int __exit ag71xx_remove(struct platform_device *pdev)
951 {
952         struct net_device *dev = platform_get_drvdata(pdev);
953
954         if (dev) {
955                 struct ag71xx *ag = netdev_priv(dev);
956
957                 ag71xx_debugfs_exit(ag);
958                 ag71xx_phy_disconnect(ag);
959                 unregister_netdev(dev);
960                 free_irq(dev->irq, dev);
961                 iounmap(ag->mii_ctrl);
962                 iounmap(ag->mac_base);
963                 kfree(dev);
964                 platform_set_drvdata(pdev, NULL);
965         }
966
967         return 0;
968 }
969
970 static struct platform_driver ag71xx_driver = {
971         .probe          = ag71xx_probe,
972         .remove         = __exit_p(ag71xx_remove),
973         .driver = {
974                 .name   = AG71XX_DRV_NAME,
975         }
976 };
977
978 static int __init ag71xx_module_init(void)
979 {
980         int ret;
981
982         ret = ag71xx_debugfs_root_init();
983         if (ret)
984                 goto err_out;
985
986         ret = ag71xx_mdio_driver_init();
987         if (ret)
988                 goto err_debugfs_exit;
989
990         ret = platform_driver_register(&ag71xx_driver);
991         if (ret)
992                 goto err_mdio_exit;
993
994         return 0;
995
996  err_mdio_exit:
997         ag71xx_mdio_driver_exit();
998  err_debugfs_exit:
999         ag71xx_debugfs_root_exit();
1000  err_out:
1001         return ret;
1002 }
1003
1004 static void __exit ag71xx_module_exit(void)
1005 {
1006         platform_driver_unregister(&ag71xx_driver);
1007         ag71xx_mdio_driver_exit();
1008         ag71xx_debugfs_root_exit();
1009 }
1010
1011 module_init(ag71xx_module_init);
1012 module_exit(ag71xx_module_exit);
1013
1014 MODULE_VERSION(AG71XX_DRV_VERSION);
1015 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1016 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1017 MODULE_LICENSE("GPL v2");
1018 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);