fc838f45b4b5c923af13e4998cdfd27838eed67a
[openwrt-10.03/.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2  *  Atheros AR71xx built-in ethernet mac driver
3  *
4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6  *
7  *  Based on Atheros' AG7100 driver
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License version 2 as published
11  *  by the Free Software Foundation.
12  */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE       \
17         ( NETIF_MSG_DRV                 \
18         | NETIF_MSG_PROBE               \
19         | NETIF_MSG_LINK                \
20         | NETIF_MSG_TIMER               \
21         | NETIF_MSG_IFDOWN              \
22         | NETIF_MSG_IFUP                \
23         | NETIF_MSG_RX_ERR              \
24         | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34                 ag->dev->name,
35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40                 ag->dev->name,
41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49                 ag->dev->name,
50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56                 ag->dev->name,
57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61                 ag->dev->name,
62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66                 ag->dev->name,
67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75                 ag->dev->name, label, intr,
76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86         kfree(ring->buf);
87
88         if (ring->descs_cpu)
89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
90                                   ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95         int err;
96         int i;
97
98         ring->desc_size = sizeof(struct ag71xx_desc);
99         if (ring->desc_size % cache_line_size()) {
100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101                         ring, ring->desc_size,
102                         roundup(ring->desc_size, cache_line_size()));
103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104         }
105
106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
107                                              &ring->descs_dma, GFP_ATOMIC);
108         if (!ring->descs_cpu) {
109                 err = -ENOMEM;
110                 goto err;
111         }
112
113         ring->size = size;
114
115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
116         if (!ring->buf) {
117                 err = -ENOMEM;
118                 goto err;
119         }
120
121         for (i = 0; i < size; i++) {
122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
123                 DBG("ag71xx: ring %p, desc %d at %p\n",
124                         ring, i, ring->buf[i].desc);
125         }
126
127         return 0;
128
129  err:
130         return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135         struct ag71xx_ring *ring = &ag->tx_ring;
136         struct net_device *dev = ag->dev;
137
138         while (ring->curr != ring->dirty) {
139                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
140
141                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142                         ring->buf[i].desc->ctrl = 0;
143                         dev->stats.tx_errors++;
144                 }
145
146                 if (ring->buf[i].skb)
147                         dev_kfree_skb_any(ring->buf[i].skb);
148
149                 ring->buf[i].skb = NULL;
150
151                 ring->dirty++;
152         }
153
154         /* flush descriptors */
155         wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161         struct ag71xx_ring *ring = &ag->tx_ring;
162         int i;
163
164         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
165                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
167
168                 ring->buf[i].desc->ctrl = DESC_EMPTY;
169                 ring->buf[i].skb = NULL;
170         }
171
172         /* flush descriptors */
173         wmb();
174
175         ring->curr = 0;
176         ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181         struct ag71xx_ring *ring = &ag->rx_ring;
182         int i;
183
184         if (!ring->buf)
185                 return;
186
187         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
188                 if (ring->buf[i].skb) {
189                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191                         kfree_skb(ring->buf[i].skb);
192                 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197         int reserve = 0;
198
199         if (ag71xx_get_pdata(ag)->is_ar724x) {
200                 if (!ag71xx_has_ar8216(ag))
201                         reserve = 2;
202
203                 if (ag->phy_dev)
204                         reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206                 reserve %= 4;
207         }
208
209         return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215         struct ag71xx_ring *ring = &ag->rx_ring;
216         unsigned int reserve = ag71xx_rx_reserve(ag);
217         unsigned int i;
218         int ret;
219
220         ret = 0;
221         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
222                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
224
225                 DBG("ag71xx: RX desc at %p, next is %08x\n",
226                         ring->buf[i].desc,
227                         ring->buf[i].desc->next);
228         }
229
230         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
231                 struct sk_buff *skb;
232                 dma_addr_t dma_addr;
233
234                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235                 if (!skb) {
236                         ret = -ENOMEM;
237                         break;
238                 }
239
240                 skb->dev = ag->dev;
241                 skb_reserve(skb, reserve);
242
243                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244                                           AG71XX_RX_PKT_SIZE,
245                                           DMA_FROM_DEVICE);
246                 ring->buf[i].skb = skb;
247                 ring->buf[i].dma_addr = dma_addr;
248                 ring->buf[i].desc->data = (u32) dma_addr;
249                 ring->buf[i].desc->ctrl = DESC_EMPTY;
250         }
251
252         /* flush descriptors */
253         wmb();
254
255         ring->curr = 0;
256         ring->dirty = 0;
257
258         return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263         struct ag71xx_ring *ring = &ag->rx_ring;
264         unsigned int reserve = ag71xx_rx_reserve(ag);
265         unsigned int count;
266
267         count = 0;
268         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269                 unsigned int i;
270
271                 i = ring->dirty % AG71XX_RX_RING_SIZE;
272
273                 if (ring->buf[i].skb == NULL) {
274                         dma_addr_t dma_addr;
275                         struct sk_buff *skb;
276
277                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278                         if (skb == NULL)
279                                 break;
280
281                         skb_reserve(skb, reserve);
282                         skb->dev = ag->dev;
283
284                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285                                                   AG71XX_RX_PKT_SIZE,
286                                                   DMA_FROM_DEVICE);
287
288                         ring->buf[i].skb = skb;
289                         ring->buf[i].dma_addr = dma_addr;
290                         ring->buf[i].desc->data = (u32) dma_addr;
291                 }
292
293                 ring->buf[i].desc->ctrl = DESC_EMPTY;
294                 count++;
295         }
296
297         /* flush descriptors */
298         wmb();
299
300         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302         return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307         int ret;
308
309         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
310         if (ret)
311                 return ret;
312
313         ag71xx_ring_tx_init(ag);
314
315         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
316         if (ret)
317                 return ret;
318
319         ret = ag71xx_ring_rx_init(ag);
320         return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325         ag71xx_ring_rx_clean(ag);
326         ag71xx_ring_free(&ag->rx_ring);
327
328         ag71xx_ring_tx_clean(ag);
329         ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334         switch (ag->speed) {
335         case SPEED_1000:
336                 return "1000";
337         case SPEED_100:
338                 return "100";
339         case SPEED_10:
340                 return "10";
341         }
342
343         return "?";
344 }
345
346 void ag71xx_link_adjust(struct ag71xx *ag)
347 {
348         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
349         u32 cfg2;
350         u32 ifctl;
351         u32 fifo5;
352         u32 mii_speed;
353
354         if (!ag->link) {
355                 netif_carrier_off(ag->dev);
356                 if (netif_msg_link(ag))
357                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
358                 return;
359         }
360
361         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
362         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
363         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
364
365         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
366         ifctl &= ~(MAC_IFCTL_SPEED);
367
368         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
369         fifo5 &= ~FIFO_CFG5_BM;
370
371         switch (ag->speed) {
372         case SPEED_1000:
373                 mii_speed =  MII_CTRL_SPEED_1000;
374                 cfg2 |= MAC_CFG2_IF_1000;
375                 fifo5 |= FIFO_CFG5_BM;
376                 break;
377         case SPEED_100:
378                 mii_speed = MII_CTRL_SPEED_100;
379                 cfg2 |= MAC_CFG2_IF_10_100;
380                 ifctl |= MAC_IFCTL_SPEED;
381                 break;
382         case SPEED_10:
383                 mii_speed = MII_CTRL_SPEED_10;
384                 cfg2 |= MAC_CFG2_IF_10_100;
385                 break;
386         default:
387                 BUG();
388                 return;
389         }
390
391         if (pdata->is_ar91xx)
392                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
393         else if (pdata->is_ar724x)
394                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
395         else
396                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
397
398         if (pdata->set_pll)
399                 pdata->set_pll(ag->speed);
400
401         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
402
403         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
404         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
405         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
406
407         netif_carrier_on(ag->dev);
408         if (netif_msg_link(ag))
409                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
410                         ag->dev->name,
411                         ag71xx_speed_str(ag),
412                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
413
414         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
415                 ag->dev->name,
416                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
417                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
418                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
419
420         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
421                 ag->dev->name,
422                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
423                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
424                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
425
426         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
427                 ag->dev->name,
428                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
429                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
430                 ag71xx_mii_ctrl_rr(ag));
431 }
432
433 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
434 {
435         u32 t;
436
437         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
438           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
439
440         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
441
442         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
443         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
444 }
445
446 static void ag71xx_dma_reset(struct ag71xx *ag)
447 {
448         u32 val;
449         int i;
450
451         ag71xx_dump_dma_regs(ag);
452
453         /* stop RX and TX */
454         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
455         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
456
457         /*
458          * give the hardware some time to really stop all rx/tx activity
459          * clearing the descriptors too early causes random memory corruption
460          */
461         mdelay(1);
462
463         /* clear descriptor addresses */
464         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
465         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
466
467         /* clear pending RX/TX interrupts */
468         for (i = 0; i < 256; i++) {
469                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
470                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
471         }
472
473         /* clear pending errors */
474         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
475         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
476
477         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
478         if (val)
479                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
480                         ag->dev->name, val);
481
482         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
483
484         /* mask out reserved bits */
485         val &= ~0xff000000;
486
487         if (val)
488                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
489                         ag->dev->name, val);
490
491         ag71xx_dump_dma_regs(ag);
492 }
493
494 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
495                          MAC_CFG1_SRX | MAC_CFG1_STX)
496
497 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
498
499 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
500                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
501                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
502                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
503                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
504                          FIFO_CFG4_VT)
505
506 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
507                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
508                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
509                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
510                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
511                          FIFO_CFG5_17 | FIFO_CFG5_SF)
512
513 static void ag71xx_hw_init(struct ag71xx *ag)
514 {
515         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
516
517         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
518         udelay(20);
519
520         ar71xx_device_stop(pdata->reset_bit);
521         mdelay(100);
522         ar71xx_device_start(pdata->reset_bit);
523         mdelay(100);
524
525         /* setup MAC configuration registers */
526         if (pdata->is_ar724x)
527                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
528                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
529         else
530                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
531
532         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
533                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
534
535         /* setup max frame length */
536         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
537
538         /* setup MII interface type */
539         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
540
541         /* setup FIFO configuration registers */
542         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
543         if (pdata->is_ar724x) {
544                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
545                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
546         } else {
547                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
548                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
549         }
550         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
551         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
552
553         ag71xx_dma_reset(ag);
554 }
555
556 static void ag71xx_hw_start(struct ag71xx *ag)
557 {
558         /* start RX engine */
559         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
560
561         /* enable interrupts */
562         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
563 }
564
565 static void ag71xx_hw_stop(struct ag71xx *ag)
566 {
567         /* disable all interrupts */
568         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
569
570         ag71xx_dma_reset(ag);
571 }
572
573 static int ag71xx_open(struct net_device *dev)
574 {
575         struct ag71xx *ag = netdev_priv(dev);
576         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
577         int ret;
578
579         ret = ag71xx_rings_init(ag);
580         if (ret)
581                 goto err;
582
583         if (pdata->is_ar724x)
584                 ag71xx_hw_init(ag);
585
586         napi_enable(&ag->napi);
587
588         netif_carrier_off(dev);
589         ag71xx_phy_start(ag);
590
591         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
592         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
593
594         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
595
596         ag71xx_hw_start(ag);
597
598         netif_start_queue(dev);
599
600         return 0;
601
602  err:
603         ag71xx_rings_cleanup(ag);
604         return ret;
605 }
606
607 static int ag71xx_stop(struct net_device *dev)
608 {
609         struct ag71xx *ag = netdev_priv(dev);
610         unsigned long flags;
611
612         netif_carrier_off(dev);
613         ag71xx_phy_stop(ag);
614
615         spin_lock_irqsave(&ag->lock, flags);
616
617         netif_stop_queue(dev);
618
619         ag71xx_hw_stop(ag);
620
621         napi_disable(&ag->napi);
622         del_timer_sync(&ag->oom_timer);
623
624         spin_unlock_irqrestore(&ag->lock, flags);
625
626         ag71xx_rings_cleanup(ag);
627
628         return 0;
629 }
630
631 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
632                                           struct net_device *dev)
633 {
634         struct ag71xx *ag = netdev_priv(dev);
635         struct ag71xx_ring *ring = &ag->tx_ring;
636         struct ag71xx_desc *desc;
637         dma_addr_t dma_addr;
638         int i;
639
640         i = ring->curr % AG71XX_TX_RING_SIZE;
641         desc = ring->buf[i].desc;
642
643         if (!ag71xx_desc_empty(desc))
644                 goto err_drop;
645
646         if (ag71xx_has_ar8216(ag))
647                 ag71xx_add_ar8216_header(ag, skb);
648
649         if (skb->len <= 0) {
650                 DBG("%s: packet len is too small\n", ag->dev->name);
651                 goto err_drop;
652         }
653
654         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
655                                   DMA_TO_DEVICE);
656
657         ring->buf[i].skb = skb;
658
659         /* setup descriptor fields */
660         desc->data = (u32) dma_addr;
661         desc->ctrl = (skb->len & DESC_PKTLEN_M);
662
663         /* flush descriptor */
664         wmb();
665
666         ring->curr++;
667         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
668                 DBG("%s: tx queue full\n", ag->dev->name);
669                 netif_stop_queue(dev);
670         }
671
672         DBG("%s: packet injected into TX queue\n", ag->dev->name);
673
674         /* enable TX engine */
675         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
676
677         return NETDEV_TX_OK;
678
679  err_drop:
680         dev->stats.tx_dropped++;
681
682         dev_kfree_skb(skb);
683         return NETDEV_TX_OK;
684 }
685
686 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
687 {
688         struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
689         struct ag71xx *ag = netdev_priv(dev);
690         int ret;
691
692         switch (cmd) {
693         case SIOCETHTOOL:
694                 if (ag->phy_dev == NULL)
695                         break;
696
697                 spin_lock_irq(&ag->lock);
698                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
699                 spin_unlock_irq(&ag->lock);
700                 return ret;
701
702         case SIOCSIFHWADDR:
703                 if (copy_from_user
704                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
705                         return -EFAULT;
706                 return 0;
707
708         case SIOCGIFHWADDR:
709                 if (copy_to_user
710                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
711                         return -EFAULT;
712                 return 0;
713
714         case SIOCGMIIPHY:
715         case SIOCGMIIREG:
716         case SIOCSMIIREG:
717                 if (ag->phy_dev == NULL)
718                         break;
719
720                 return phy_mii_ioctl(ag->phy_dev, data, cmd);
721
722         default:
723                 break;
724         }
725
726         return -EOPNOTSUPP;
727 }
728
729 static void ag71xx_oom_timer_handler(unsigned long data)
730 {
731         struct net_device *dev = (struct net_device *) data;
732         struct ag71xx *ag = netdev_priv(dev);
733
734         napi_schedule(&ag->napi);
735 }
736
737 static void ag71xx_tx_timeout(struct net_device *dev)
738 {
739         struct ag71xx *ag = netdev_priv(dev);
740
741         if (netif_msg_tx_err(ag))
742                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
743
744         schedule_work(&ag->restart_work);
745 }
746
747 static void ag71xx_restart_work_func(struct work_struct *work)
748 {
749         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
750
751         ag71xx_stop(ag->dev);
752         ag71xx_open(ag->dev);
753 }
754
755 static int ag71xx_tx_packets(struct ag71xx *ag)
756 {
757         struct ag71xx_ring *ring = &ag->tx_ring;
758         int sent;
759
760         DBG("%s: processing TX ring\n", ag->dev->name);
761
762         sent = 0;
763         while (ring->dirty != ring->curr) {
764                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
765                 struct ag71xx_desc *desc = ring->buf[i].desc;
766                 struct sk_buff *skb = ring->buf[i].skb;
767
768                 if (!ag71xx_desc_empty(desc))
769                         break;
770
771                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
772
773                 ag->dev->stats.tx_bytes += skb->len;
774                 ag->dev->stats.tx_packets++;
775
776                 dev_kfree_skb_any(skb);
777                 ring->buf[i].skb = NULL;
778
779                 ring->dirty++;
780                 sent++;
781         }
782
783         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
784
785         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
786                 netif_wake_queue(ag->dev);
787
788         return sent;
789 }
790
791 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
792 {
793         struct net_device *dev = ag->dev;
794         struct ag71xx_ring *ring = &ag->rx_ring;
795         int done = 0;
796
797         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
798                         dev->name, limit, ring->curr, ring->dirty);
799
800         while (done < limit) {
801                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
802                 struct ag71xx_desc *desc = ring->buf[i].desc;
803                 struct sk_buff *skb;
804                 int pktlen;
805                 int err = 0;
806
807                 if (ag71xx_desc_empty(desc))
808                         break;
809
810                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
811                         ag71xx_assert(0);
812                         break;
813                 }
814
815                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
816
817                 skb = ring->buf[i].skb;
818                 pktlen = ag71xx_desc_pktlen(desc);
819                 pktlen -= ETH_FCS_LEN;
820
821                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
822                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
823
824                 dev->last_rx = jiffies;
825                 dev->stats.rx_packets++;
826                 dev->stats.rx_bytes += pktlen;
827
828                 skb_put(skb, pktlen);
829                 if (ag71xx_has_ar8216(ag))
830                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
831
832                 if (err) {
833                         dev->stats.rx_dropped++;
834                         kfree_skb(skb);
835                 } else {
836                         skb->dev = dev;
837                         skb->ip_summed = CHECKSUM_NONE;
838                         if (ag->phy_dev) {
839                                 ag->phy_dev->netif_receive_skb(skb);
840                         } else {
841                                 skb->protocol = eth_type_trans(skb, dev);
842                                 netif_receive_skb(skb);
843                         }
844                 }
845
846                 ring->buf[i].skb = NULL;
847                 done++;
848
849                 ring->curr++;
850         }
851
852         ag71xx_ring_rx_refill(ag);
853
854         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
855                 dev->name, ring->curr, ring->dirty, done);
856
857         return done;
858 }
859
860 static int ag71xx_poll(struct napi_struct *napi, int limit)
861 {
862         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
863         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
864         struct net_device *dev = ag->dev;
865         struct ag71xx_ring *rx_ring;
866         unsigned long flags;
867         u32 status;
868         int tx_done;
869         int rx_done;
870
871         pdata->ddr_flush();
872         tx_done = ag71xx_tx_packets(ag);
873
874         DBG("%s: processing RX ring\n", dev->name);
875         rx_done = ag71xx_rx_packets(ag, limit);
876
877         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
878
879         rx_ring = &ag->rx_ring;
880         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
881                 goto oom;
882
883         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
884         if (unlikely(status & RX_STATUS_OF)) {
885                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
886                 dev->stats.rx_fifo_errors++;
887
888                 /* restart RX */
889                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
890         }
891
892         if (rx_done < limit) {
893                 if (status & RX_STATUS_PR)
894                         goto more;
895
896                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
897                 if (status & TX_STATUS_PS)
898                         goto more;
899
900                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
901                         dev->name, rx_done, tx_done, limit);
902
903                 napi_complete(napi);
904
905                 /* enable interrupts */
906                 spin_lock_irqsave(&ag->lock, flags);
907                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
908                 spin_unlock_irqrestore(&ag->lock, flags);
909                 return rx_done;
910         }
911
912  more:
913         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
914                         dev->name, rx_done, tx_done, limit);
915         return rx_done;
916
917  oom:
918         if (netif_msg_rx_err(ag))
919                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
920
921         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
922         napi_complete(napi);
923         return 0;
924 }
925
926 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
927 {
928         struct net_device *dev = dev_id;
929         struct ag71xx *ag = netdev_priv(dev);
930         u32 status;
931
932         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
933         ag71xx_dump_intr(ag, "raw", status);
934
935         if (unlikely(!status))
936                 return IRQ_NONE;
937
938         if (unlikely(status & AG71XX_INT_ERR)) {
939                 if (status & AG71XX_INT_TX_BE) {
940                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
941                         dev_err(&dev->dev, "TX BUS error\n");
942                 }
943                 if (status & AG71XX_INT_RX_BE) {
944                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
945                         dev_err(&dev->dev, "RX BUS error\n");
946                 }
947         }
948
949         if (likely(status & AG71XX_INT_POLL)) {
950                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
951                 DBG("%s: enable polling mode\n", dev->name);
952                 napi_schedule(&ag->napi);
953         }
954
955         ag71xx_debugfs_update_int_stats(ag, status);
956
957         return IRQ_HANDLED;
958 }
959
960 static void ag71xx_set_multicast_list(struct net_device *dev)
961 {
962         /* TODO */
963 }
964
965 #ifdef CONFIG_NET_POLL_CONTROLLER
966 /*
967  * Polling 'interrupt' - used by things like netconsole to send skbs
968  * without having to re-enable interrupts. It's not called while
969  * the interrupt routine is executing.
970  */
971 static void ag71xx_netpoll(struct net_device *dev)
972 {
973         disable_irq(dev->irq);
974         ag71xx_interrupt(dev->irq, dev);
975         enable_irq(dev->irq);
976 }
977 #endif
978
979 static const struct net_device_ops ag71xx_netdev_ops = {
980         .ndo_open               = ag71xx_open,
981         .ndo_stop               = ag71xx_stop,
982         .ndo_start_xmit         = ag71xx_hard_start_xmit,
983         .ndo_set_multicast_list = ag71xx_set_multicast_list,
984         .ndo_do_ioctl           = ag71xx_do_ioctl,
985         .ndo_tx_timeout         = ag71xx_tx_timeout,
986         .ndo_change_mtu         = eth_change_mtu,
987         .ndo_set_mac_address    = eth_mac_addr,
988         .ndo_validate_addr      = eth_validate_addr,
989 #ifdef CONFIG_NET_POLL_CONTROLLER
990         .ndo_poll_controller    = ag71xx_netpoll,
991 #endif
992 };
993
994 static int __init ag71xx_probe(struct platform_device *pdev)
995 {
996         struct net_device *dev;
997         struct resource *res;
998         struct ag71xx *ag;
999         struct ag71xx_platform_data *pdata;
1000         int err;
1001
1002         pdata = pdev->dev.platform_data;
1003         if (!pdata) {
1004                 dev_err(&pdev->dev, "no platform data specified\n");
1005                 err = -ENXIO;
1006                 goto err_out;
1007         }
1008
1009         if (pdata->mii_bus_dev == NULL) {
1010                 dev_err(&pdev->dev, "no MII bus device specified\n");
1011                 err = -EINVAL;
1012                 goto err_out;
1013         }
1014
1015         dev = alloc_etherdev(sizeof(*ag));
1016         if (!dev) {
1017                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1018                 err = -ENOMEM;
1019                 goto err_out;
1020         }
1021
1022         SET_NETDEV_DEV(dev, &pdev->dev);
1023
1024         ag = netdev_priv(dev);
1025         ag->pdev = pdev;
1026         ag->dev = dev;
1027         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1028                                         AG71XX_DEFAULT_MSG_ENABLE);
1029         spin_lock_init(&ag->lock);
1030
1031         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1032         if (!res) {
1033                 dev_err(&pdev->dev, "no mac_base resource found\n");
1034                 err = -ENXIO;
1035                 goto err_out;
1036         }
1037
1038         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1039         if (!ag->mac_base) {
1040                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1041                 err = -ENOMEM;
1042                 goto err_free_dev;
1043         }
1044
1045         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1046         if (!res) {
1047                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1048                 err = -ENXIO;
1049                 goto err_unmap_base;
1050         }
1051
1052         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1053         if (!ag->mii_ctrl) {
1054                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1055                 err = -ENOMEM;
1056                 goto err_unmap_base;
1057         }
1058
1059         dev->irq = platform_get_irq(pdev, 0);
1060         err = request_irq(dev->irq, ag71xx_interrupt,
1061                           IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
1062                           dev->name, dev);
1063         if (err) {
1064                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1065                 goto err_unmap_mii_ctrl;
1066         }
1067
1068         dev->base_addr = (unsigned long)ag->mac_base;
1069         dev->netdev_ops = &ag71xx_netdev_ops;
1070         dev->ethtool_ops = &ag71xx_ethtool_ops;
1071
1072         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1073
1074         init_timer(&ag->oom_timer);
1075         ag->oom_timer.data = (unsigned long) dev;
1076         ag->oom_timer.function = ag71xx_oom_timer_handler;
1077
1078         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1079
1080         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1081
1082         err = register_netdev(dev);
1083         if (err) {
1084                 dev_err(&pdev->dev, "unable to register net device\n");
1085                 goto err_free_irq;
1086         }
1087
1088         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1089                dev->name, dev->base_addr, dev->irq);
1090
1091         ag71xx_dump_regs(ag);
1092
1093         ag71xx_hw_init(ag);
1094
1095         ag71xx_dump_regs(ag);
1096
1097         err = ag71xx_phy_connect(ag);
1098         if (err)
1099                 goto err_unregister_netdev;
1100
1101         err = ag71xx_debugfs_init(ag);
1102         if (err)
1103                 goto err_phy_disconnect;
1104
1105         platform_set_drvdata(pdev, dev);
1106
1107         return 0;
1108
1109  err_phy_disconnect:
1110         ag71xx_phy_disconnect(ag);
1111  err_unregister_netdev:
1112         unregister_netdev(dev);
1113  err_free_irq:
1114         free_irq(dev->irq, dev);
1115  err_unmap_mii_ctrl:
1116         iounmap(ag->mii_ctrl);
1117  err_unmap_base:
1118         iounmap(ag->mac_base);
1119  err_free_dev:
1120         kfree(dev);
1121  err_out:
1122         platform_set_drvdata(pdev, NULL);
1123         return err;
1124 }
1125
1126 static int __exit ag71xx_remove(struct platform_device *pdev)
1127 {
1128         struct net_device *dev = platform_get_drvdata(pdev);
1129
1130         if (dev) {
1131                 struct ag71xx *ag = netdev_priv(dev);
1132
1133                 ag71xx_debugfs_exit(ag);
1134                 ag71xx_phy_disconnect(ag);
1135                 unregister_netdev(dev);
1136                 free_irq(dev->irq, dev);
1137                 iounmap(ag->mii_ctrl);
1138                 iounmap(ag->mac_base);
1139                 kfree(dev);
1140                 platform_set_drvdata(pdev, NULL);
1141         }
1142
1143         return 0;
1144 }
1145
1146 static struct platform_driver ag71xx_driver = {
1147         .probe          = ag71xx_probe,
1148         .remove         = __exit_p(ag71xx_remove),
1149         .driver = {
1150                 .name   = AG71XX_DRV_NAME,
1151         }
1152 };
1153
1154 static int __init ag71xx_module_init(void)
1155 {
1156         int ret;
1157
1158         ret = ag71xx_debugfs_root_init();
1159         if (ret)
1160                 goto err_out;
1161
1162         ret = ag71xx_mdio_driver_init();
1163         if (ret)
1164                 goto err_debugfs_exit;
1165
1166         ret = platform_driver_register(&ag71xx_driver);
1167         if (ret)
1168                 goto err_mdio_exit;
1169
1170         return 0;
1171
1172  err_mdio_exit:
1173         ag71xx_mdio_driver_exit();
1174  err_debugfs_exit:
1175         ag71xx_debugfs_root_exit();
1176  err_out:
1177         return ret;
1178 }
1179
1180 static void __exit ag71xx_module_exit(void)
1181 {
1182         platform_driver_unregister(&ag71xx_driver);
1183         ag71xx_mdio_driver_exit();
1184         ag71xx_debugfs_root_exit();
1185 }
1186
1187 module_init(ag71xx_module_init);
1188 module_exit(ag71xx_module_exit);
1189
1190 MODULE_VERSION(AG71XX_DRV_VERSION);
1191 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1192 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1193 MODULE_LICENSE("GPL v2");
1194 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);