eae443e8ceea8ff84ea35f7201870e04a8a28908
[openwrt-10.03/.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2  *  Atheros AR71xx built-in ethernet mac driver
3  *
4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6  *
7  *  Based on Atheros' AG7100 driver
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License version 2 as published
11  *  by the Free Software Foundation.
12  */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE       \
17         (NETIF_MSG_DRV                  \
18         | NETIF_MSG_PROBE               \
19         | NETIF_MSG_LINK                \
20         | NETIF_MSG_TIMER               \
21         | NETIF_MSG_IFDOWN              \
22         | NETIF_MSG_IFUP                \
23         | NETIF_MSG_RX_ERR              \
24         | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34                 ag->dev->name,
35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40                 ag->dev->name,
41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49                 ag->dev->name,
50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56                 ag->dev->name,
57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61                 ag->dev->name,
62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66                 ag->dev->name,
67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75                 ag->dev->name, label, intr,
76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86         kfree(ring->buf);
87
88         if (ring->descs_cpu)
89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
90                                   ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95         int err;
96         int i;
97
98         ring->desc_size = sizeof(struct ag71xx_desc);
99         if (ring->desc_size % cache_line_size()) {
100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101                         ring, ring->desc_size,
102                         roundup(ring->desc_size, cache_line_size()));
103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104         }
105
106         ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size,
107                                              &ring->descs_dma, GFP_ATOMIC);
108         if (!ring->descs_cpu) {
109                 err = -ENOMEM;
110                 goto err;
111         }
112
113         ring->size = size;
114
115         ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
116         if (!ring->buf) {
117                 err = -ENOMEM;
118                 goto err;
119         }
120
121         for (i = 0; i < size; i++) {
122                 int idx = i * ring->desc_size;
123                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
124                 DBG("ag71xx: ring %p, desc %d at %p\n",
125                         ring, i, ring->buf[i].desc);
126         }
127
128         return 0;
129
130 err:
131         return err;
132 }
133
134 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 {
136         struct ag71xx_ring *ring = &ag->tx_ring;
137         struct net_device *dev = ag->dev;
138
139         while (ring->curr != ring->dirty) {
140                 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
141
142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143                         ring->buf[i].desc->ctrl = 0;
144                         dev->stats.tx_errors++;
145                 }
146
147                 if (ring->buf[i].skb)
148                         dev_kfree_skb_any(ring->buf[i].skb);
149
150                 ring->buf[i].skb = NULL;
151
152                 ring->dirty++;
153         }
154
155         /* flush descriptors */
156         wmb();
157
158 }
159
160 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 {
162         struct ag71xx_ring *ring = &ag->tx_ring;
163         int i;
164
165         for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
166                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
167                         ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE));
168
169                 ring->buf[i].desc->ctrl = DESC_EMPTY;
170                 ring->buf[i].skb = NULL;
171         }
172
173         /* flush descriptors */
174         wmb();
175
176         ring->curr = 0;
177         ring->dirty = 0;
178 }
179
180 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
181 {
182         struct ag71xx_ring *ring = &ag->rx_ring;
183         int i;
184
185         if (!ring->buf)
186                 return;
187
188         for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
189                 if (ring->buf[i].skb) {
190                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
191                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
192                         kfree_skb(ring->buf[i].skb);
193                 }
194 }
195
196 static int ag71xx_rx_reserve(struct ag71xx *ag)
197 {
198         int reserve = 0;
199
200         if (ag71xx_get_pdata(ag)->is_ar724x) {
201                 if (!ag71xx_has_ar8216(ag))
202                         reserve = 2;
203
204                 if (ag->phy_dev)
205                         reserve += 4 - (ag->phy_dev->pkt_align % 4);
206
207                 reserve %= 4;
208         }
209
210         return reserve + AG71XX_RX_PKT_RESERVE;
211 }
212
213
214 static int ag71xx_ring_rx_init(struct ag71xx *ag)
215 {
216         struct ag71xx_ring *ring = &ag->rx_ring;
217         unsigned int reserve = ag71xx_rx_reserve(ag);
218         unsigned int i;
219         int ret;
220
221         ret = 0;
222         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
223                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
224                         ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE));
225
226                 DBG("ag71xx: RX desc at %p, next is %08x\n",
227                         ring->buf[i].desc,
228                         ring->buf[i].desc->next);
229         }
230
231         for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
232                 struct sk_buff *skb;
233                 dma_addr_t dma_addr;
234
235                 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
236                 if (!skb) {
237                         ret = -ENOMEM;
238                         break;
239                 }
240
241                 skb->dev = ag->dev;
242                 skb_reserve(skb, reserve);
243
244                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
245                                           AG71XX_RX_PKT_SIZE,
246                                           DMA_FROM_DEVICE);
247                 ring->buf[i].skb = skb;
248                 ring->buf[i].dma_addr = dma_addr;
249                 ring->buf[i].desc->data = (u32) dma_addr;
250                 ring->buf[i].desc->ctrl = DESC_EMPTY;
251         }
252
253         /* flush descriptors */
254         wmb();
255
256         ring->curr = 0;
257         ring->dirty = 0;
258
259         return ret;
260 }
261
262 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
263 {
264         struct ag71xx_ring *ring = &ag->rx_ring;
265         unsigned int reserve = ag71xx_rx_reserve(ag);
266         unsigned int count;
267
268         count = 0;
269         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
270                 unsigned int i;
271
272                 i = ring->dirty % AG71XX_RX_RING_SIZE;
273
274                 if (ring->buf[i].skb == NULL) {
275                         dma_addr_t dma_addr;
276                         struct sk_buff *skb;
277
278                         skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
279                         if (skb == NULL)
280                                 break;
281
282                         skb_reserve(skb, reserve);
283                         skb->dev = ag->dev;
284
285                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
286                                                   AG71XX_RX_PKT_SIZE,
287                                                   DMA_FROM_DEVICE);
288
289                         ring->buf[i].skb = skb;
290                         ring->buf[i].dma_addr = dma_addr;
291                         ring->buf[i].desc->data = (u32) dma_addr;
292                 }
293
294                 ring->buf[i].desc->ctrl = DESC_EMPTY;
295                 count++;
296         }
297
298         /* flush descriptors */
299         wmb();
300
301         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
302
303         return count;
304 }
305
306 static int ag71xx_rings_init(struct ag71xx *ag)
307 {
308         int ret;
309
310         ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
311         if (ret)
312                 return ret;
313
314         ag71xx_ring_tx_init(ag);
315
316         ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
317         if (ret)
318                 return ret;
319
320         ret = ag71xx_ring_rx_init(ag);
321         return ret;
322 }
323
324 static void ag71xx_rings_cleanup(struct ag71xx *ag)
325 {
326         ag71xx_ring_rx_clean(ag);
327         ag71xx_ring_free(&ag->rx_ring);
328
329         ag71xx_ring_tx_clean(ag);
330         ag71xx_ring_free(&ag->tx_ring);
331 }
332
333 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
334 {
335         switch (ag->speed) {
336         case SPEED_1000:
337                 return "1000";
338         case SPEED_100:
339                 return "100";
340         case SPEED_10:
341                 return "10";
342         }
343
344         return "?";
345 }
346
347 void ag71xx_link_adjust(struct ag71xx *ag)
348 {
349         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
350         u32 cfg2;
351         u32 ifctl;
352         u32 fifo5;
353         u32 mii_speed;
354
355         if (!ag->link) {
356                 netif_carrier_off(ag->dev);
357                 if (netif_msg_link(ag))
358                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
359                 return;
360         }
361
362         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
363         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
364         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
365
366         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
367         ifctl &= ~(MAC_IFCTL_SPEED);
368
369         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
370         fifo5 &= ~FIFO_CFG5_BM;
371
372         switch (ag->speed) {
373         case SPEED_1000:
374                 mii_speed =  MII_CTRL_SPEED_1000;
375                 cfg2 |= MAC_CFG2_IF_1000;
376                 fifo5 |= FIFO_CFG5_BM;
377                 break;
378         case SPEED_100:
379                 mii_speed = MII_CTRL_SPEED_100;
380                 cfg2 |= MAC_CFG2_IF_10_100;
381                 ifctl |= MAC_IFCTL_SPEED;
382                 break;
383         case SPEED_10:
384                 mii_speed = MII_CTRL_SPEED_10;
385                 cfg2 |= MAC_CFG2_IF_10_100;
386                 break;
387         default:
388                 BUG();
389                 return;
390         }
391
392         if (pdata->is_ar91xx)
393                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
394         else if (pdata->is_ar724x)
395                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
396         else
397                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
398
399         if (pdata->set_pll)
400                 pdata->set_pll(ag->speed);
401
402         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
403
404         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
405         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
406         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
407
408         netif_carrier_on(ag->dev);
409         if (netif_msg_link(ag))
410                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
411                         ag->dev->name,
412                         ag71xx_speed_str(ag),
413                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
414
415         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
416                 ag->dev->name,
417                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
418                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
419                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
420
421         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
422                 ag->dev->name,
423                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
424                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
425                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
426
427         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
428                 ag->dev->name,
429                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
430                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
431                 ag71xx_mii_ctrl_rr(ag));
432 }
433
434 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
435 {
436         u32 t;
437
438         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
439           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
440
441         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
442
443         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
444         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
445 }
446
447 static void ag71xx_dma_reset(struct ag71xx *ag)
448 {
449         u32 val;
450         int i;
451
452         ag71xx_dump_dma_regs(ag);
453
454         /* stop RX and TX */
455         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
456         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
457
458         /*
459          * give the hardware some time to really stop all rx/tx activity
460          * clearing the descriptors too early causes random memory corruption
461          */
462         mdelay(1);
463
464         /* clear descriptor addresses */
465         ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
466         ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
467
468         /* clear pending RX/TX interrupts */
469         for (i = 0; i < 256; i++) {
470                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
471                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
472         }
473
474         /* clear pending errors */
475         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
476         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
477
478         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
479         if (val)
480                 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
481                         ag->dev->name, val);
482
483         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
484
485         /* mask out reserved bits */
486         val &= ~0xff000000;
487
488         if (val)
489                 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
490                         ag->dev->name, val);
491
492         ag71xx_dump_dma_regs(ag);
493 }
494
495 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
496                          MAC_CFG1_SRX | MAC_CFG1_STX)
497
498 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
499
500 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
501                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
502                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
503                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
504                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
505                          FIFO_CFG4_VT)
506
507 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
508                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
509                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
510                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
511                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
512                          FIFO_CFG5_17 | FIFO_CFG5_SF)
513
514 static void ag71xx_hw_init(struct ag71xx *ag)
515 {
516         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
517
518         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
519         udelay(20);
520
521         ar71xx_device_stop(pdata->reset_bit);
522         mdelay(100);
523         ar71xx_device_start(pdata->reset_bit);
524         mdelay(100);
525
526         /* setup MAC configuration registers */
527         if (pdata->is_ar724x)
528                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
529                           MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC);
530         else
531                 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
532
533         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
534                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
535
536         /* setup max frame length */
537         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
538
539         /* setup MII interface type */
540         ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
541
542         /* setup FIFO configuration registers */
543         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
544         if (pdata->is_ar724x) {
545                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
546                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
547         } else {
548                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
549                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
550         }
551         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
552         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
553
554         ag71xx_dma_reset(ag);
555 }
556
557 static void ag71xx_hw_start(struct ag71xx *ag)
558 {
559         /* start RX engine */
560         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
561
562         /* enable interrupts */
563         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
564 }
565
566 static void ag71xx_hw_stop(struct ag71xx *ag)
567 {
568         /* disable all interrupts */
569         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
570
571         ag71xx_dma_reset(ag);
572 }
573
574 static int ag71xx_open(struct net_device *dev)
575 {
576         struct ag71xx *ag = netdev_priv(dev);
577         int ret;
578
579         ret = ag71xx_rings_init(ag);
580         if (ret)
581                 goto err;
582
583         napi_enable(&ag->napi);
584
585         netif_carrier_off(dev);
586         ag71xx_phy_start(ag);
587
588         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
589         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
590
591         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
592
593         ag71xx_hw_start(ag);
594
595         netif_start_queue(dev);
596
597         return 0;
598
599 err:
600         ag71xx_rings_cleanup(ag);
601         return ret;
602 }
603
604 static int ag71xx_stop(struct net_device *dev)
605 {
606         struct ag71xx *ag = netdev_priv(dev);
607         unsigned long flags;
608
609         netif_carrier_off(dev);
610         ag71xx_phy_stop(ag);
611
612         spin_lock_irqsave(&ag->lock, flags);
613
614         netif_stop_queue(dev);
615
616         ag71xx_hw_stop(ag);
617
618         napi_disable(&ag->napi);
619         del_timer_sync(&ag->oom_timer);
620
621         spin_unlock_irqrestore(&ag->lock, flags);
622
623         ag71xx_rings_cleanup(ag);
624
625         return 0;
626 }
627
628 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
629                                           struct net_device *dev)
630 {
631         struct ag71xx *ag = netdev_priv(dev);
632         struct ag71xx_ring *ring = &ag->tx_ring;
633         struct ag71xx_desc *desc;
634         dma_addr_t dma_addr;
635         int i;
636
637         i = ring->curr % AG71XX_TX_RING_SIZE;
638         desc = ring->buf[i].desc;
639
640         if (!ag71xx_desc_empty(desc))
641                 goto err_drop;
642
643         if (ag71xx_has_ar8216(ag))
644                 ag71xx_add_ar8216_header(ag, skb);
645
646         if (skb->len <= 0) {
647                 DBG("%s: packet len is too small\n", ag->dev->name);
648                 goto err_drop;
649         }
650
651         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
652                                   DMA_TO_DEVICE);
653
654         ring->buf[i].skb = skb;
655
656         /* setup descriptor fields */
657         desc->data = (u32) dma_addr;
658         desc->ctrl = (skb->len & DESC_PKTLEN_M);
659
660         /* flush descriptor */
661         wmb();
662
663         ring->curr++;
664         if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
665                 DBG("%s: tx queue full\n", ag->dev->name);
666                 netif_stop_queue(dev);
667         }
668
669         DBG("%s: packet injected into TX queue\n", ag->dev->name);
670
671         /* enable TX engine */
672         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
673
674         return NETDEV_TX_OK;
675
676 err_drop:
677         dev->stats.tx_dropped++;
678
679         dev_kfree_skb(skb);
680         return NETDEV_TX_OK;
681 }
682
683 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
684 {
685         struct ag71xx *ag = netdev_priv(dev);
686         int ret;
687
688         switch (cmd) {
689         case SIOCETHTOOL:
690                 if (ag->phy_dev == NULL)
691                         break;
692
693                 spin_lock_irq(&ag->lock);
694                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
695                 spin_unlock_irq(&ag->lock);
696                 return ret;
697
698         case SIOCSIFHWADDR:
699                 if (copy_from_user
700                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
701                         return -EFAULT;
702                 return 0;
703
704         case SIOCGIFHWADDR:
705                 if (copy_to_user
706                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
707                         return -EFAULT;
708                 return 0;
709
710         case SIOCGMIIPHY:
711         case SIOCGMIIREG:
712         case SIOCSMIIREG:
713                 if (ag->phy_dev == NULL)
714                         break;
715
716                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
717
718         default:
719                 break;
720         }
721
722         return -EOPNOTSUPP;
723 }
724
725 static void ag71xx_oom_timer_handler(unsigned long data)
726 {
727         struct net_device *dev = (struct net_device *) data;
728         struct ag71xx *ag = netdev_priv(dev);
729
730         napi_schedule(&ag->napi);
731 }
732
733 static void ag71xx_tx_timeout(struct net_device *dev)
734 {
735         struct ag71xx *ag = netdev_priv(dev);
736
737         if (netif_msg_tx_err(ag))
738                 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
739
740         schedule_work(&ag->restart_work);
741 }
742
743 static void ag71xx_restart_work_func(struct work_struct *work)
744 {
745         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
746         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
747
748         ag71xx_stop(ag->dev);
749
750         if (pdata->is_ar724x)
751                 ag71xx_hw_init(ag);
752
753         ag71xx_open(ag->dev);
754 }
755
756 static int ag71xx_tx_packets(struct ag71xx *ag)
757 {
758         struct ag71xx_ring *ring = &ag->tx_ring;
759         int sent;
760
761         DBG("%s: processing TX ring\n", ag->dev->name);
762
763         sent = 0;
764         while (ring->dirty != ring->curr) {
765                 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
766                 struct ag71xx_desc *desc = ring->buf[i].desc;
767                 struct sk_buff *skb = ring->buf[i].skb;
768
769                 if (!ag71xx_desc_empty(desc))
770                         break;
771
772                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
773
774                 ag->dev->stats.tx_bytes += skb->len;
775                 ag->dev->stats.tx_packets++;
776
777                 dev_kfree_skb_any(skb);
778                 ring->buf[i].skb = NULL;
779
780                 ring->dirty++;
781                 sent++;
782         }
783
784         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
785
786         if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
787                 netif_wake_queue(ag->dev);
788
789         return sent;
790 }
791
792 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
793 {
794         struct net_device *dev = ag->dev;
795         struct ag71xx_ring *ring = &ag->rx_ring;
796         int done = 0;
797
798         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
799                         dev->name, limit, ring->curr, ring->dirty);
800
801         while (done < limit) {
802                 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
803                 struct ag71xx_desc *desc = ring->buf[i].desc;
804                 struct sk_buff *skb;
805                 int pktlen;
806                 int err = 0;
807
808                 if (ag71xx_desc_empty(desc))
809                         break;
810
811                 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
812                         ag71xx_assert(0);
813                         break;
814                 }
815
816                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
817
818                 skb = ring->buf[i].skb;
819                 pktlen = ag71xx_desc_pktlen(desc);
820                 pktlen -= ETH_FCS_LEN;
821
822                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
823                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
824
825                 dev->last_rx = jiffies;
826                 dev->stats.rx_packets++;
827                 dev->stats.rx_bytes += pktlen;
828
829                 skb_put(skb, pktlen);
830                 if (ag71xx_has_ar8216(ag))
831                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
832
833                 if (err) {
834                         dev->stats.rx_dropped++;
835                         kfree_skb(skb);
836                 } else {
837                         skb->dev = dev;
838                         skb->ip_summed = CHECKSUM_NONE;
839                         if (ag->phy_dev) {
840                                 ag->phy_dev->netif_receive_skb(skb);
841                         } else {
842                                 skb->protocol = eth_type_trans(skb, dev);
843                                 netif_receive_skb(skb);
844                         }
845                 }
846
847                 ring->buf[i].skb = NULL;
848                 done++;
849
850                 ring->curr++;
851         }
852
853         ag71xx_ring_rx_refill(ag);
854
855         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
856                 dev->name, ring->curr, ring->dirty, done);
857
858         return done;
859 }
860
861 static int ag71xx_poll(struct napi_struct *napi, int limit)
862 {
863         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
864         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
865         struct net_device *dev = ag->dev;
866         struct ag71xx_ring *rx_ring;
867         unsigned long flags;
868         u32 status;
869         int tx_done;
870         int rx_done;
871
872         pdata->ddr_flush();
873         tx_done = ag71xx_tx_packets(ag);
874
875         DBG("%s: processing RX ring\n", dev->name);
876         rx_done = ag71xx_rx_packets(ag, limit);
877
878         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
879
880         rx_ring = &ag->rx_ring;
881         if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
882                 goto oom;
883
884         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
885         if (unlikely(status & RX_STATUS_OF)) {
886                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
887                 dev->stats.rx_fifo_errors++;
888
889                 /* restart RX */
890                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
891         }
892
893         if (rx_done < limit) {
894                 if (status & RX_STATUS_PR)
895                         goto more;
896
897                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
898                 if (status & TX_STATUS_PS)
899                         goto more;
900
901                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
902                         dev->name, rx_done, tx_done, limit);
903
904                 napi_complete(napi);
905
906                 /* enable interrupts */
907                 spin_lock_irqsave(&ag->lock, flags);
908                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
909                 spin_unlock_irqrestore(&ag->lock, flags);
910                 return rx_done;
911         }
912
913 more:
914         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
915                         dev->name, rx_done, tx_done, limit);
916         return rx_done;
917
918 oom:
919         if (netif_msg_rx_err(ag))
920                 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
921
922         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
923         napi_complete(napi);
924         return 0;
925 }
926
927 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
928 {
929         struct net_device *dev = dev_id;
930         struct ag71xx *ag = netdev_priv(dev);
931         u32 status;
932
933         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
934         ag71xx_dump_intr(ag, "raw", status);
935
936         if (unlikely(!status))
937                 return IRQ_NONE;
938
939         if (unlikely(status & AG71XX_INT_ERR)) {
940                 if (status & AG71XX_INT_TX_BE) {
941                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
942                         dev_err(&dev->dev, "TX BUS error\n");
943                 }
944                 if (status & AG71XX_INT_RX_BE) {
945                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
946                         dev_err(&dev->dev, "RX BUS error\n");
947                 }
948         }
949
950         if (likely(status & AG71XX_INT_POLL)) {
951                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
952                 DBG("%s: enable polling mode\n", dev->name);
953                 napi_schedule(&ag->napi);
954         }
955
956         ag71xx_debugfs_update_int_stats(ag, status);
957
958         return IRQ_HANDLED;
959 }
960
961 static void ag71xx_set_multicast_list(struct net_device *dev)
962 {
963         /* TODO */
964 }
965
966 #ifdef CONFIG_NET_POLL_CONTROLLER
967 /*
968  * Polling 'interrupt' - used by things like netconsole to send skbs
969  * without having to re-enable interrupts. It's not called while
970  * the interrupt routine is executing.
971  */
972 static void ag71xx_netpoll(struct net_device *dev)
973 {
974         disable_irq(dev->irq);
975         ag71xx_interrupt(dev->irq, dev);
976         enable_irq(dev->irq);
977 }
978 #endif
979
980 static const struct net_device_ops ag71xx_netdev_ops = {
981         .ndo_open               = ag71xx_open,
982         .ndo_stop               = ag71xx_stop,
983         .ndo_start_xmit         = ag71xx_hard_start_xmit,
984         .ndo_set_multicast_list = ag71xx_set_multicast_list,
985         .ndo_do_ioctl           = ag71xx_do_ioctl,
986         .ndo_tx_timeout         = ag71xx_tx_timeout,
987         .ndo_change_mtu         = eth_change_mtu,
988         .ndo_set_mac_address    = eth_mac_addr,
989         .ndo_validate_addr      = eth_validate_addr,
990 #ifdef CONFIG_NET_POLL_CONTROLLER
991         .ndo_poll_controller    = ag71xx_netpoll,
992 #endif
993 };
994
995 static int __devinit ag71xx_probe(struct platform_device *pdev)
996 {
997         struct net_device *dev;
998         struct resource *res;
999         struct ag71xx *ag;
1000         struct ag71xx_platform_data *pdata;
1001         int err;
1002
1003         pdata = pdev->dev.platform_data;
1004         if (!pdata) {
1005                 dev_err(&pdev->dev, "no platform data specified\n");
1006                 err = -ENXIO;
1007                 goto err_out;
1008         }
1009
1010         if (pdata->mii_bus_dev == NULL) {
1011                 dev_err(&pdev->dev, "no MII bus device specified\n");
1012                 err = -EINVAL;
1013                 goto err_out;
1014         }
1015
1016         dev = alloc_etherdev(sizeof(*ag));
1017         if (!dev) {
1018                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1019                 err = -ENOMEM;
1020                 goto err_out;
1021         }
1022
1023         SET_NETDEV_DEV(dev, &pdev->dev);
1024
1025         ag = netdev_priv(dev);
1026         ag->pdev = pdev;
1027         ag->dev = dev;
1028         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1029                                         AG71XX_DEFAULT_MSG_ENABLE);
1030         spin_lock_init(&ag->lock);
1031
1032         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1033         if (!res) {
1034                 dev_err(&pdev->dev, "no mac_base resource found\n");
1035                 err = -ENXIO;
1036                 goto err_out;
1037         }
1038
1039         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1040         if (!ag->mac_base) {
1041                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1042                 err = -ENOMEM;
1043                 goto err_free_dev;
1044         }
1045
1046         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1047         if (!res) {
1048                 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1049                 err = -ENXIO;
1050                 goto err_unmap_base;
1051         }
1052
1053         ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1054         if (!ag->mii_ctrl) {
1055                 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1056                 err = -ENOMEM;
1057                 goto err_unmap_base;
1058         }
1059
1060         dev->irq = platform_get_irq(pdev, 0);
1061         err = request_irq(dev->irq, ag71xx_interrupt,
1062                           IRQF_DISABLED,
1063                           dev->name, dev);
1064         if (err) {
1065                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1066                 goto err_unmap_mii_ctrl;
1067         }
1068
1069         dev->base_addr = (unsigned long)ag->mac_base;
1070         dev->netdev_ops = &ag71xx_netdev_ops;
1071         dev->ethtool_ops = &ag71xx_ethtool_ops;
1072
1073         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1074
1075         init_timer(&ag->oom_timer);
1076         ag->oom_timer.data = (unsigned long) dev;
1077         ag->oom_timer.function = ag71xx_oom_timer_handler;
1078
1079         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1080
1081         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1082
1083         err = register_netdev(dev);
1084         if (err) {
1085                 dev_err(&pdev->dev, "unable to register net device\n");
1086                 goto err_free_irq;
1087         }
1088
1089         printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1090                dev->name, dev->base_addr, dev->irq);
1091
1092         ag71xx_dump_regs(ag);
1093
1094         ag71xx_hw_init(ag);
1095
1096         ag71xx_dump_regs(ag);
1097
1098         err = ag71xx_phy_connect(ag);
1099         if (err)
1100                 goto err_unregister_netdev;
1101
1102