package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S

   1 /*
   2  * IFX Platform Dependent CPU Initializations
   3  * - for Danube
   4  */
   5
   6 #define IFX_EBU_BOOTCFG_DWORD                                                   \
   7         .word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \
   8         .word 0x00000000;           /* phases of the flash */
   9
  10 #define IFX_MORE_RESERVED_VECTORS                                               \
  11         XVECENT(romExcHandle,0x400);    /* Int, CauseIV=1 */                    \
  12         RVECENT(romReserved,129);                                               \
  13         RVECENT(romReserved,130);                                               \
  14         RVECENT(romReserved,131);                                               \
  15         RVECENT(romReserved,132);                                               \
  16         RVECENT(romReserved,133);                                               \
  17         RVECENT(romReserved,134);                                               \
  18         RVECENT(romReserved,135);                                               \
  19         RVECENT(romReserved,136);                                               \
  20         RVECENT(romReserved,137);                                               \
  21         RVECENT(romReserved,138);                                               \
  22         RVECENT(romReserved,139);                                               \
  23         RVECENT(romReserved,140);                                               \
  24         RVECENT(romReserved,141);                                               \
  25         RVECENT(romReserved,142);                                               \
  26         RVECENT(romReserved,143);                                               \
  27         RVECENT(romExcHandle,0x480);    /* EJTAG debug exception */
  28
  29 #define IFX_RESET_PRECHECK                                                      \
  30         mfc0    k0, CP0_EBASE;                                                  \
  31         and     k0, EBASEF_CPUNUM;                                              \
  32         bne     k0, zero, ifx_mips_handler_1;                                   \
  33         nop;
  34
  35 #define IFX_CPU_EXTRA_INIT                                                      \
  36         mfc0    k0, CP0_CONFIG, 7;                                              \
  37         li      k1, 0x04;                                                       \
  38         or      k0, k1;                                                         \
  39         mtc0    k0, CP0_CONFIG, 7;
  40
  41 #define IFX_CACHE_OPER_MODE                                                     \
  42         li      t0, CONF_CM_CACHABLE_NO_WA;
  43
  44 /*
  45  * Stop VCPU
  46  */
  47 #define IFX_MIPS_HANDLER_1                                                      \
  48         wait;                                                                   \
  49         b ifx_mips_handler_1;                                                   \
  50         nop;
  51