From 4c2c7dc3541eabf5674e607a6ad139168e44c66e Mon Sep 17 00:00:00 2001 From: Alexandros Couloumbis Date: Wed, 11 Nov 2020 13:15:35 +0200 Subject: [PATCH] wifi ozonet updates --- .../files-4.4/drivers/net/phy/ar8216.c | 88 +++++++++---------- .../files-4.4/drivers/net/phy/ar8327.c | 78 +++------------- 2 files changed, 56 insertions(+), 110 deletions(-) diff --git a/target/linux/generic/files-4.4/drivers/net/phy/ar8216.c b/target/linux/generic/files-4.4/drivers/net/phy/ar8216.c index 7512ee1b43..27b062bc47 100644 --- a/target/linux/generic/files-4.4/drivers/net/phy/ar8216.c +++ b/target/linux/generic/files-4.4/drivers/net/phy/ar8216.c @@ -177,7 +177,7 @@ ar8xxx_phy_check_aneg(struct phy_device *phydev) if (ret & BMCR_ANENABLE) return 0; - dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n"); + dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n"); ret |= BMCR_ANENABLE | BMCR_ANRESTART; return phy_write(phydev, MII_BMCR, ret); } @@ -355,7 +355,6 @@ ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val, return 0; usleep_range(1000, 2000); - cond_resched(); } return -ETIMEDOUT; @@ -427,7 +426,6 @@ ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush) mib_stats[i] = 0; else mib_stats[i] += t; - cond_resched(); } } @@ -567,7 +565,6 @@ ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val) break; udelay(10); - cond_resched(); } pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n", @@ -733,10 +730,8 @@ ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) { int timeout = 20; - while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) { - udelay(10); - cond_resched(); - } + while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) + udelay(10); if (!timeout) pr_err("ar8216: timeout waiting for atu to become ready\n"); @@ -1199,7 +1194,6 @@ ar8xxx_sw_reset_switch(struct switch_dev *dev) priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME; chip->init_globals(priv); - chip->atu_flush(priv); mutex_unlock(&priv->reg_mutex); @@ -1701,16 +1695,6 @@ static const struct switch_dev_ops ar8xxx_sw_ops = { .apply_config = ar8xxx_sw_hw_apply, .reset_switch = ar8xxx_sw_reset_switch, .get_port_link = ar8xxx_sw_get_port_link, -/* The following op is disabled as it hogs the CPU and degrades performance. - An implementation has been attempted in 4d8a66d but reading MIB data is slow - on ar8xxx switches. - - The high CPU load has been traced down to the ar8xxx_reg_wait() call in - ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by - the request to update the MIB counter is cleared. */ -#if 0 - .get_port_stats = ar8xxx_sw_get_port_stats, -#endif }; static const struct ar8xxx_chip ar8216_chip = { @@ -2012,7 +1996,7 @@ ar8xxx_phy_config_init(struct phy_device *phydev) priv->phy = phydev; - if (phydev->mdio.addr != 0) { + if (phydev->addr != 0) { if (chip_is_ar8316(priv)) { /* switch device has been initialized, reinit */ priv->dev.ports = (AR8216_NUM_PORTS - 1); @@ -2060,7 +2044,7 @@ ar8xxx_check_link_states(struct ar8xxx_priv *priv) /* flush ARL entries for this port if it went down*/ if (!link_new) priv->chip->atu_flush_port(priv, i); - dev_info(&priv->phy->mdio.dev, "Port %d is %s\n", + dev_info(&priv->phy->dev, "Port %d is %s\n", i, link_new ? "up" : "down"); } @@ -2079,10 +2063,10 @@ ar8xxx_phy_read_status(struct phy_device *phydev) if (phydev->state == PHY_CHANGELINK) ar8xxx_check_link_states(priv); - if (phydev->mdio.addr != 0) + if (phydev->addr != 0) return genphy_read_status(phydev); - ar8216_read_port_link(priv, phydev->mdio.addr, &link); + ar8216_read_port_link(priv, phydev->addr, &link); phydev->link = !!link.link; if (!phydev->link) return 0; @@ -2112,7 +2096,7 @@ ar8xxx_phy_read_status(struct phy_device *phydev) static int ar8xxx_phy_config_aneg(struct phy_device *phydev) { - if (phydev->mdio.addr == 0) + if (phydev->addr == 0) return 0; return genphy_config_aneg(phydev); @@ -2167,15 +2151,15 @@ ar8xxx_phy_probe(struct phy_device *phydev) int ret; /* skip PHYs at unused adresses */ - if (phydev->mdio.addr != 0 && phydev->mdio.addr != 4) + if (phydev->addr != 0 && phydev->addr != 4) return -ENODEV; - if (!ar8xxx_is_possible(phydev->mdio.bus)) + if (!ar8xxx_is_possible(phydev->bus)) return -ENODEV; mutex_lock(&ar8xxx_dev_list_lock); list_for_each_entry(priv, &ar8xxx_dev_list, list) - if (priv->mii_bus == phydev->mdio.bus) + if (priv->mii_bus == phydev->bus) goto found; priv = ar8xxx_create(); @@ -2184,7 +2168,7 @@ ar8xxx_phy_probe(struct phy_device *phydev) goto unlock; } - priv->mii_bus = phydev->mdio.bus; + priv->mii_bus = phydev->bus; ret = ar8xxx_probe_switch(priv); if (ret) @@ -2205,7 +2189,7 @@ ar8xxx_phy_probe(struct phy_device *phydev) found: priv->use_count++; - if (phydev->mdio.addr == 0) { + if (phydev->addr == 0) { if (ar8xxx_has_gige(priv)) { phydev->supported = SUPPORTED_1000baseT_Full; phydev->advertising = ADVERTISED_1000baseT_Full; @@ -2286,28 +2270,44 @@ ar8xxx_phy_remove(struct phy_device *phydev) ar8xxx_free(priv); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) static int ar8xxx_phy_soft_reset(struct phy_device *phydev) { /* we don't need an extra reset */ return 0; } +#endif -static struct phy_driver ar8xxx_phy_driver[] = { - { - .phy_id = 0x004d0000, - .name = "Atheros AR8216/AR8236/AR8316", - .phy_id_mask = 0xffff0000, - .features = PHY_BASIC_FEATURES, - .probe = ar8xxx_phy_probe, - .remove = ar8xxx_phy_remove, - .detach = ar8xxx_phy_detach, - .config_init = ar8xxx_phy_config_init, - .config_aneg = ar8xxx_phy_config_aneg, - .read_status = ar8xxx_phy_read_status, - .soft_reset = ar8xxx_phy_soft_reset, - } +static struct phy_driver ar8xxx_phy_driver = { + .phy_id = 0x004d0000, + .name = "Atheros AR8216/AR8236/AR8316", + .phy_id_mask = 0xffff0000, + .features = PHY_BASIC_FEATURES, + .probe = ar8xxx_phy_probe, + .remove = ar8xxx_phy_remove, + .detach = ar8xxx_phy_detach, + .config_init = ar8xxx_phy_config_init, + .config_aneg = ar8xxx_phy_config_aneg, + .read_status = ar8xxx_phy_read_status, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) + .soft_reset = ar8xxx_phy_soft_reset, +#endif + .driver = { .owner = THIS_MODULE }, }; -module_phy_driver(ar8xxx_phy_driver); +int __init +ar8xxx_init(void) +{ + return phy_driver_register(&ar8xxx_phy_driver); +} + +void __exit +ar8xxx_exit(void) +{ + phy_driver_unregister(&ar8xxx_phy_driver); +} + +module_init(ar8xxx_init); +module_exit(ar8xxx_exit); MODULE_LICENSE("GPL"); diff --git a/target/linux/generic/files-4.4/drivers/net/phy/ar8327.c b/target/linux/generic/files-4.4/drivers/net/phy/ar8327.c index 74f0a08d76..72e0abc9d6 100644 --- a/target/linux/generic/files-4.4/drivers/net/phy/ar8327.c +++ b/target/linux/generic/files-4.4/drivers/net/phy/ar8327.c @@ -619,11 +619,11 @@ ar8327_hw_init(struct ar8xxx_priv *priv) if (!priv->chip_data) return -ENOMEM; - if (priv->phy->mdio.dev.of_node) - ret = ar8327_hw_config_of(priv, priv->phy->mdio.dev.of_node); + if (priv->phy->dev.of_node) + ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node); else ret = ar8327_hw_config_pdata(priv, - priv->phy->mdio.dev.platform_data); + priv->phy->dev.platform_data); if (ret) return ret; @@ -885,19 +885,10 @@ ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members) t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S; t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S; - if (priv->vlan && priv->port_vlan_prio[port]) { - u32 prio = priv->port_vlan_prio[port]; - - t |= prio << AR8327_PORT_VLAN0_DEF_SPRI_S; - t |= prio << AR8327_PORT_VLAN0_DEF_CPRI_S; - } ar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t); t = AR8327_PORT_VLAN1_PORT_VLAN_PROP; t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S; - if (priv->vlan && priv->port_vlan_prio[port]) - t |= AR8327_PORT_VLAN1_VLAN_PRI_PROP; - ar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t); t = members; @@ -1042,15 +1033,14 @@ ar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1) { int timeout = 20; - while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) { - udelay(10); - cond_resched(); - } + while (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) + udelay(10); if (!timeout) pr_err("ar8327: timeout waiting for atu to become ready\n"); } +#if 0 static void ar8327_get_arl_entry(struct ar8xxx_priv *priv, struct arl_entry *a, u32 *status, enum arl_op op) { @@ -1110,6 +1100,7 @@ static void ar8327_get_arl_entry(struct ar8xxx_priv *priv, break; } } +#endif static int ar8327_sw_hw_apply(struct switch_dev *dev) @@ -1238,37 +1229,6 @@ ar8327_sw_set_igmp_v3(struct switch_dev *dev, return 0; } -static int -ar8327_sw_set_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr, - struct switch_val *val) -{ - struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); - int port = val->port_vlan; - - if (port >= dev->ports) - return -EINVAL; - if (port == 0 || port == 6) - return -EOPNOTSUPP; - if (val->value.i < 0 || val->value.i > 7) - return -EINVAL; - - priv->port_vlan_prio[port] = val->value.i; - - return 0; -} - -static int -ar8327_sw_get_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr, - struct switch_val *val) -{ - struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev); - int port = val->port_vlan; - - val->value.i = priv->port_vlan_prio[port]; - - return 0; -} - static const struct switch_attr ar8327_sw_attr_globals[] = { { .type = SWITCH_TYPE_INT, @@ -1315,7 +1275,7 @@ static const struct switch_attr ar8327_sw_attr_globals[] = { .set = ar8xxx_sw_set_mirror_source_port, .get = ar8xxx_sw_get_mirror_source_port, .max = AR8327_NUM_PORTS - 1 - }, + }, { .type = SWITCH_TYPE_INT, .name = "arl_age_time", @@ -1390,14 +1350,6 @@ static const struct switch_attr ar8327_sw_attr_port[] = { .get = ar8327_sw_get_port_igmp_snooping, .max = 1 }, - { - .type = SWITCH_TYPE_INT, - .name = "vlan_prio", - .description = "Port VLAN default priority (VLAN PCP) (0-7)", - .set = ar8327_sw_set_port_vlan_prio, - .get = ar8327_sw_get_port_vlan_prio, - .max = 7, - }, }; static const struct switch_dev_ops ar8327_sw_ops = { @@ -1420,16 +1372,6 @@ static const struct switch_dev_ops ar8327_sw_ops = { .apply_config = ar8327_sw_hw_apply, .reset_switch = ar8xxx_sw_reset_switch, .get_port_link = ar8xxx_sw_get_port_link, -/* The following op is disabled as it hogs the CPU and degrades performance. - An implementation has been attempted in 4d8a66d but reading MIB data is slow - on ar8xxx switches. - - The high CPU load has been traced down to the ar8xxx_reg_wait() call in - ar8xxx_mib_op(), which has to usleep_range() till the MIB busy flag set by - the request to update the MIB counter is cleared. */ -#if 0 - .get_port_stats = ar8xxx_sw_get_port_stats, -#endif }; const struct ar8xxx_chip ar8327_chip = { @@ -1459,7 +1401,9 @@ const struct ar8xxx_chip ar8327_chip = { .vtu_load_vlan = ar8327_vtu_load_vlan, .phy_fixup = ar8327_phy_fixup, .set_mirror_regs = ar8327_set_mirror_regs, +#if 0 .get_arl_entry = ar8327_get_arl_entry, +#endif .sw_hw_apply = ar8327_sw_hw_apply, .num_mibs = ARRAY_SIZE(ar8236_mibs), @@ -1494,7 +1438,9 @@ const struct ar8xxx_chip ar8337_chip = { .vtu_load_vlan = ar8327_vtu_load_vlan, .phy_fixup = ar8327_phy_fixup, .set_mirror_regs = ar8327_set_mirror_regs, +#if 0 .get_arl_entry = ar8327_get_arl_entry, +#endif .sw_hw_apply = ar8327_sw_hw_apply, .num_mibs = ARRAY_SIZE(ar8236_mibs), -- 2.35.1