--- /dev/null
+From 8f09588b2cdc2dfb6e6076fd10708791d6c6bedd Mon Sep 17 00:00:00 2001
+From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Date: Mon, 23 May 2016 23:12:43 +0300
+Subject: ath10k: move rx_location_info out of struct rx_pkt_end
+
+Define rx_location_info in struct rx_ppdu_end_qca99x0 after
+rx_pkt_end. This is to prepare rx_ppdu_end for QCA9984 chip.
+
+Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath10k/rx_desc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/wireless/ath/ath10k/rx_desc.h b/drivers/net/wireless/ath/ath10k/rx_desc.h
+index ca8d168..3e7dfaa 100644
+--- a/drivers/net/wireless/ath/ath10k/rx_desc.h
++++ b/drivers/net/wireless/ath/ath10k/rx_desc.h
+@@ -994,7 +994,6 @@ struct rx_pkt_end {
+ __le32 info0; /* %RX_PKT_END_INFO0_ */
+ __le32 phy_timestamp_1;
+ __le32 phy_timestamp_2;
+- __le32 rx_location_info; /* %RX_LOCATION_INFO_ */
+ } __packed;
+
+ enum rx_phy_ppdu_end_info0 {
+@@ -1067,6 +1066,7 @@ struct rx_phy_ppdu_end {
+
+ struct rx_ppdu_end_qca99x0 {
+ struct rx_pkt_end rx_pkt_end;
++ __le32 rx_location_info; /* %RX_LOCATION_INFO_ */
+ struct rx_phy_ppdu_end rx_phy_ppdu_end;
+ __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */
+ __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */
+--
+cgit v0.12
+
--- /dev/null
+From 0fc7e270523bf3757687e930c02bb46e3dcedde9 Mon Sep 17 00:00:00 2001
+From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Date: Mon, 23 May 2016 23:12:43 +0300
+Subject: ath10k: clean up growing hw checks during safe and full reset
+
+Store pci chip secific reset funtions in struct ath10k_pci
+as callbacks during early ath10k_pci_probe() and use the
+callback to perform chip specific resets. This patch essentially
+adds two callback in ath10k_pci, one for doing soft reset and
+the other for hard reset. By using callbacks we can get rid of
+those hw revision checks in ath10k_pci_safe_chip_reset() and
+ath10k_pci_chip_reset(). As such this patch does not fix
+any issue.
+
+Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath10k/pci.c | 44 ++++++++++++++++++++++-------------
+ drivers/net/wireless/ath/ath10k/pci.h | 6 +++++
+ 2 files changed, 34 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
+index 8133d7b..81d6bad 100644
+--- a/drivers/net/wireless/ath/ath10k/pci.c
++++ b/drivers/net/wireless/ath/ath10k/pci.c
+@@ -2293,16 +2293,20 @@ static int ath10k_pci_warm_reset(struct ath10k *ar)
+ return 0;
+ }
+
++static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
++{
++ ath10k_pci_irq_disable(ar);
++ return ath10k_pci_qca99x0_chip_reset(ar);
++}
++
+ static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
+ {
+- if (QCA_REV_988X(ar) || QCA_REV_6174(ar)) {
+- return ath10k_pci_warm_reset(ar);
+- } else if (QCA_REV_99X0(ar)) {
+- ath10k_pci_irq_disable(ar);
+- return ath10k_pci_qca99x0_chip_reset(ar);
+- } else {
++ struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
++
++ if (!ar_pci->pci_soft_reset)
+ return -ENOTSUPP;
+- }
++
++ return ar_pci->pci_soft_reset(ar);
+ }
+
+ static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
+@@ -2437,16 +2441,12 @@ static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
+
+ static int ath10k_pci_chip_reset(struct ath10k *ar)
+ {
+- if (QCA_REV_988X(ar))
+- return ath10k_pci_qca988x_chip_reset(ar);
+- else if (QCA_REV_6174(ar))
+- return ath10k_pci_qca6174_chip_reset(ar);
+- else if (QCA_REV_9377(ar))
+- return ath10k_pci_qca6174_chip_reset(ar);
+- else if (QCA_REV_99X0(ar))
+- return ath10k_pci_qca99x0_chip_reset(ar);
+- else
++ struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
++
++ if (WARN_ON(!ar_pci->pci_hard_reset))
+ return -ENOTSUPP;
++
++ return ar_pci->pci_hard_reset(ar);
+ }
+
+ static int ath10k_pci_hif_power_up(struct ath10k *ar)
+@@ -2976,24 +2976,34 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
+ enum ath10k_hw_rev hw_rev;
+ u32 chip_id;
+ bool pci_ps;
++ int (*pci_soft_reset)(struct ath10k *ar);
++ int (*pci_hard_reset)(struct ath10k *ar);
+
+ switch (pci_dev->device) {
+ case QCA988X_2_0_DEVICE_ID:
+ hw_rev = ATH10K_HW_QCA988X;
+ pci_ps = false;
++ pci_soft_reset = ath10k_pci_warm_reset;
++ pci_hard_reset = ath10k_pci_qca988x_chip_reset;
+ break;
+ case QCA6164_2_1_DEVICE_ID:
+ case QCA6174_2_1_DEVICE_ID:
+ hw_rev = ATH10K_HW_QCA6174;
+ pci_ps = true;
++ pci_soft_reset = ath10k_pci_warm_reset;
++ pci_hard_reset = ath10k_pci_qca6174_chip_reset;
+ break;
+ case QCA99X0_2_0_DEVICE_ID:
+ hw_rev = ATH10K_HW_QCA99X0;
+ pci_ps = false;
++ pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
++ pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
+ break;
+ case QCA9377_1_0_DEVICE_ID:
+ hw_rev = ATH10K_HW_QCA9377;
+ pci_ps = true;
++ pci_soft_reset = NULL;
++ pci_hard_reset = ath10k_pci_qca6174_chip_reset;
+ break;
+ default:
+ WARN_ON(1);
+@@ -3018,6 +3028,8 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
+ ar->dev_id = pci_dev->device;
+ ar_pci->pci_ps = pci_ps;
+ ar_pci->bus_ops = &ath10k_pci_bus_ops;
++ ar_pci->pci_soft_reset = pci_soft_reset;
++ ar_pci->pci_hard_reset = pci_hard_reset;
+
+ ar->id.vendor = pdev->vendor;
+ ar->id.device = pdev->device;
+diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h
+index 959dc32..6eca1df 100644
+--- a/drivers/net/wireless/ath/ath10k/pci.h
++++ b/drivers/net/wireless/ath/ath10k/pci.h
+@@ -234,6 +234,12 @@ struct ath10k_pci {
+
+ const struct ath10k_bus_ops *bus_ops;
+
++ /* Chip specific pci reset routine used to do a safe reset */
++ int (*pci_soft_reset)(struct ath10k *ar);
++
++ /* Chip specific pci full reset function */
++ int (*pci_hard_reset)(struct ath10k *ar);
++
+ /* Keep this entry in the last, memory for struct ath10k_ahb is
+ * allocated (ahb support enabled case) in the continuation of
+ * this struct.
+--
+cgit v0.12
+
--- /dev/null
+From acc6b5593eee9386b209dd29da1e4bdbba99cf9a Mon Sep 17 00:00:00 2001
+From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Date: Mon, 23 May 2016 23:12:44 +0300
+Subject: ath10k: define rx_ppdu_end for QCA9984
+
+QCA9984 Rx descriptor has two 32-bit words of location information
+when compared to one 32-bit word in QCA99X0. To handle this difference in
+rx descriptor ppdu_end, define a new ppdu_end for QCA9984 descriptor
+which has the new structure to represent rx_location_info.
+
+Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath10k/rx_desc.h | 46 +++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/drivers/net/wireless/ath/ath10k/rx_desc.h b/drivers/net/wireless/ath/ath10k/rx_desc.h
+index 3e7dfaa..9ceebea 100644
+--- a/drivers/net/wireless/ath/ath10k/rx_desc.h
++++ b/drivers/net/wireless/ath/ath10k/rx_desc.h
+@@ -996,6 +996,41 @@ struct rx_pkt_end {
+ __le32 phy_timestamp_2;
+ } __packed;
+
++#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK 0x00003fff
++#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB 0
++#define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK 0x1fff8000
++#define RX_LOCATION_INFO0_RTT_FAC_VHT_LSB 15
++#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK 0xc0000000
++#define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB 30
++#define RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS BIT(14)
++#define RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS BIT(29)
++
++#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK 0x0000000c
++#define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB 2
++#define RX_LOCATION_INFO1_PKT_BW_MASK 0x00000030
++#define RX_LOCATION_INFO1_PKT_BW_LSB 4
++#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK 0x0000ff00
++#define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB 8
++#define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK 0x000f0000
++#define RX_LOCATION_INFO1_RTT_MSC_RATE_LSB 16
++#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK 0x00300000
++#define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB 20
++#define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK 0x07c00000
++#define RX_LOCATION_INFO1_TIMING_BACKOFF_LSB 22
++#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK 0x18000000
++#define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB 27
++#define RX_LOCATION_INFO1_RTT_CFR_STATUS BIT(0)
++#define RX_LOCATION_INFO1_RTT_CIR_STATUS BIT(1)
++#define RX_LOCATION_INFO1_RTT_GI_TYPE BIT(7)
++#define RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE BIT(29)
++#define RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE BIT(30)
++#define RX_LOCATION_INFO1_RX_LOCATION_VALID BIT(31)
++
++struct rx_location_info {
++ __le32 rx_location_info0; /* %RX_LOCATION_INFO0_ */
++ __le32 rx_location_info1; /* %RX_LOCATION_INFO1_ */
++} __packed;
++
+ enum rx_phy_ppdu_end_info0 {
+ RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2),
+ RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3),
+@@ -1074,12 +1109,23 @@ struct rx_ppdu_end_qca99x0 {
+ __le16 info1; /* %RX_PPDU_END_INFO1_ */
+ } __packed;
+
++struct rx_ppdu_end_qca9984 {
++ struct rx_pkt_end rx_pkt_end;
++ struct rx_location_info rx_location_info;
++ struct rx_phy_ppdu_end rx_phy_ppdu_end;
++ __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */
++ __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */
++ __le16 bb_length;
++ __le16 info1; /* %RX_PPDU_END_INFO1_ */
++} __packed;
++
+ struct rx_ppdu_end {
+ struct rx_ppdu_end_common common;
+ union {
+ struct rx_ppdu_end_qca988x qca988x;
+ struct rx_ppdu_end_qca6174 qca6174;
+ struct rx_ppdu_end_qca99x0 qca99x0;
++ struct rx_ppdu_end_qca9984 qca9984;
+ } __packed;
+ } __packed;
+
+--
+cgit v0.12
+
--- /dev/null
+From 651b4cdcf97e75f6346784b75ca7bf3c85187143 Mon Sep 17 00:00:00 2001
+From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Date: Mon, 23 May 2016 23:12:45 +0300
+Subject: ath10k: enable support for QCA9984
+
+QCA9984 shares the same configuration with QCA99X0.
+
+Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
+Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath10k/core.c | 23 +++++++++++++++++++++++
+ drivers/net/wireless/ath/ath10k/hw.h | 11 +++++++++++
+ drivers/net/wireless/ath/ath10k/pci.c | 14 ++++++++++++++
+ 3 files changed, 48 insertions(+)
+
+diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
+index 49af624..a003980 100644
+--- a/drivers/net/wireless/ath/ath10k/core.c
++++ b/drivers/net/wireless/ath/ath10k/core.c
+@@ -163,6 +163,28 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
+ },
+ },
+ {
++ .id = QCA9984_HW_1_0_DEV_VERSION,
++ .dev_id = QCA9984_1_0_DEVICE_ID,
++ .name = "qca9984/qca9994 hw1.0",
++ .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
++ .uart_pin = 7,
++ .otp_exe_param = 0x00000700,
++ .continuous_frag_desc = true,
++ .channel_counters_freq_hz = 150000,
++ .max_probe_resp_desc_thres = 24,
++ .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
++ .tx_chain_mask = 0xf,
++ .rx_chain_mask = 0xf,
++ .max_spatial_stream = 4,
++ .cal_data_len = 12064,
++ .fw = {
++ .dir = QCA9984_HW_1_0_FW_DIR,
++ .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
++ .board_size = QCA99X0_BOARD_DATA_SZ,
++ .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
++ },
++ },
++ {
+ .id = QCA9377_HW_1_0_DEV_VERSION,
+ .dev_id = QCA9377_1_0_DEVICE_ID,
+ .name = "qca9377 hw1.0",
+@@ -2071,6 +2093,7 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
+ ar->hw_values = &qca6174_values;
+ break;
+ case ATH10K_HW_QCA99X0:
++ case ATH10K_HW_QCA9984:
+ ar->regs = &qca99x0_regs;
+ ar->hw_values = &qca99x0_values;
+ break;
+diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
+index aedd898..f41c91c 100644
+--- a/drivers/net/wireless/ath/ath10k/hw.h
++++ b/drivers/net/wireless/ath/ath10k/hw.h
+@@ -26,6 +26,7 @@
+ #define QCA6164_2_1_DEVICE_ID (0x0041)
+ #define QCA6174_2_1_DEVICE_ID (0x003e)
+ #define QCA99X0_2_0_DEVICE_ID (0x0040)
++#define QCA9984_1_0_DEVICE_ID (0x0046)
+ #define QCA9377_1_0_DEVICE_ID (0x0042)
+
+ /* QCA988X 1.0 definitions (unsupported) */
+@@ -91,6 +92,14 @@ enum qca9377_chip_id_rev {
+ #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
+ #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
+
++/* QCA9984 1.0 defines */
++#define QCA9984_HW_1_0_DEV_VERSION 0x1000000
++#define QCA9984_HW_DEV_TYPE 0xa
++#define QCA9984_HW_1_0_CHIP_ID_REV 0x0
++#define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0"
++#define QCA9984_HW_1_0_BOARD_DATA_FILE "board.bin"
++#define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234
++
+ /* QCA9377 1.0 definitions */
+ #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
+ #define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
+@@ -193,6 +202,7 @@ enum ath10k_hw_rev {
+ ATH10K_HW_QCA988X,
+ ATH10K_HW_QCA6174,
+ ATH10K_HW_QCA99X0,
++ ATH10K_HW_QCA9984,
+ ATH10K_HW_QCA9377,
+ ATH10K_HW_QCA4019,
+ };
+@@ -249,6 +259,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
+ #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
+ #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
+ #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
++#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
+ #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
+ #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
+
+diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
+index 81d6bad..8e8e1eb 100644
+--- a/drivers/net/wireless/ath/ath10k/pci.c
++++ b/drivers/net/wireless/ath/ath10k/pci.c
+@@ -56,6 +56,7 @@ static const struct pci_device_id ath10k_pci_id_table[] = {
+ { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
+ { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
+ { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
++ { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
+ { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
+ {0}
+ };
+@@ -81,8 +82,11 @@ static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
+
+ { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
+
++ { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
++
+ { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
+ { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
++
+ };
+
+ static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
+@@ -844,6 +848,7 @@ static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
+ 0x7ff) << 21;
+ break;
+ case ATH10K_HW_QCA99X0:
++ case ATH10K_HW_QCA9984:
+ case ATH10K_HW_QCA4019:
+ val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
+ break;
+@@ -1569,6 +1574,7 @@ static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
+ CORE_CTRL_ADDRESS, val);
+ break;
+ case ATH10K_HW_QCA99X0:
++ case ATH10K_HW_QCA9984:
+ case ATH10K_HW_QCA4019:
+ /* TODO: Find appropriate register configuration for QCA99X0
+ * to mask irq/MSI.
+@@ -1592,6 +1598,7 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
+ CORE_CTRL_ADDRESS, val);
+ break;
+ case ATH10K_HW_QCA99X0:
++ case ATH10K_HW_QCA9984:
+ case ATH10K_HW_QCA4019:
+ /* TODO: Find appropriate register configuration for QCA99X0
+ * to unmask irq/MSI.
+@@ -1932,6 +1939,7 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
+ switch (ar_pci->pdev->device) {
+ case QCA988X_2_0_DEVICE_ID:
+ case QCA99X0_2_0_DEVICE_ID:
++ case QCA9984_1_0_DEVICE_ID:
+ return 1;
+ case QCA6164_2_1_DEVICE_ID:
+ case QCA6174_2_1_DEVICE_ID:
+@@ -2999,6 +3007,12 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
+ pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
+ pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
+ break;
++ case QCA9984_1_0_DEVICE_ID:
++ hw_rev = ATH10K_HW_QCA9984;
++ pci_ps = false;
++ pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
++ pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
++ break;
+ case QCA9377_1_0_DEVICE_ID:
+ hw_rev = ATH10K_HW_QCA9377;
+ pci_ps = true;
+--
+cgit v0.12
+
--- /dev/null
+From e809ea07e9edefc3678ad0b356a95f0c4c7f27e7 Mon Sep 17 00:00:00 2001
+From: Ashok Raj Nagarajan <arnagara@qti.qualcomm.com>
+Date: Tue, 26 Jul 2016 22:15:52 +0530
+Subject: ath10k: fix get rx_status from htt context
+
+On handling amsdu on rx path, get the rx_status from htt context. Without this
+fix, we are seeing warnings when running DBDC traffic like this.
+
+WARNING: CPU: 0 PID: 0 at net/mac80211/rx.c:4105 ieee80211_rx_napi+0x88/0x7d8 [mac80211]()
+
+[ 1715.878248] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.18.21 #1
+[ 1715.878273] [<c001d3f4>] (unwind_backtrace) from [<c001a4b0>] (show_stack+0x10/0x14)
+[ 1715.878293] [<c001a4b0>] (show_stack) from [<c01bee64>] (dump_stack+0x70/0xbc)
+[ 1715.878315] [<c01bee64>] (dump_stack) from [<c002a61c>] (warn_slowpath_common+0x64/0x88)
+[ 1715.878339] [<c002a61c>] (warn_slowpath_common) from [<c002a6d0>] (warn_slowpath_null+0x18/0x20)
+[ 1715.878395] [<c002a6d0>] (warn_slowpath_null) from [<bf4caa98>] (ieee80211_rx_napi+0x88/0x7d8 [mac80211])
+[ 1715.878474] [<bf4caa98>] (ieee80211_rx_napi [mac80211]) from [<bf568658>] (ath10k_htt_t2h_msg_handler+0xb48/0xbfc [ath10k_core])
+[ 1715.878535] [<bf568658>] (ath10k_htt_t2h_msg_handler [ath10k_core]) from [<bf568708>] (ath10k_htt_t2h_msg_handler+0xbf8/0xbfc [ath10k_core])
+[ 1715.878597] [<bf568708>] (ath10k_htt_t2h_msg_handler [ath10k_core]) from [<bf569160>] (ath10k_htt_txrx_compl_task+0xa54/0x1170 [ath10k_core])
+[ 1715.878639] [<bf569160>] (ath10k_htt_txrx_compl_task [ath10k_core]) from [<c002db14>] (tasklet_action+0xb4/0x130)
+[ 1715.878659] [<c002db14>] (tasklet_action) from [<c002d110>] (__do_softirq+0xe0/0x210)
+[ 1715.878678] [<c002d110>] (__do_softirq) from [<c002d4b4>] (irq_exit+0x84/0xe0)
+[ 1715.878700] [<c002d4b4>] (irq_exit) from [<c005a544>] (__handle_domain_irq+0x98/0xd0)
+[ 1715.878722] [<c005a544>] (__handle_domain_irq) from [<c00085f4>] (gic_handle_irq+0x38/0x5c)
+[ 1715.878741] [<c00085f4>] (gic_handle_irq) from [<c0009680>] (__irq_svc+0x40/0x74)
+[ 1715.878753] Exception stack(0xc05f9f50 to 0xc05f9f98)
+[ 1715.878767] 9f40: ffffffed 00000000 00399e1e c000a220
+[ 1715.878786] 9f60: 00000000 c05f6780 c05f8000 00000000 c05f5db8 ffffffed c05f8000 c04d1980
+[ 1715.878802] 9f80: 00000000 c05f9f98 c0018110 c0018114 60000013 ffffffff
+[ 1715.878822] [<c0009680>] (__irq_svc) from [<c0018114>] (arch_cpu_idle+0x2c/0x50)
+[ 1715.878844] [<c0018114>] (arch_cpu_idle) from [<c00530d4>] (cpu_startup_entry+0x108/0x234)
+[ 1715.878866] [<c00530d4>] (cpu_startup_entry) from [<c05c7be0>] (start_kernel+0x33c/0x3b8)
+[ 1715.878879] ---[ end trace 6d5e1cc0fef8ed6a ]---
+[ 1715.878899] ------------[ cut here ]------------
+
+Fixes: 18235664e7f9 ("ath10k: cleanup amsdu processing for rx indication")
+Signed-off-by: Ashok Raj Nagarajan <arnagara@qti.qualcomm.com>
+Patchwork-Id: 9248457
+Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
+---
+ drivers/net/wireless/ath/ath10k/htt_rx.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c
+index 78db5d6..24c8d65 100644
+--- a/drivers/net/wireless/ath/ath10k/htt_rx.c
++++ b/drivers/net/wireless/ath/ath10k/htt_rx.c
+@@ -1525,7 +1525,7 @@ static void ath10k_htt_rx_h_filter(struct ath10k *ar,
+ static int ath10k_htt_rx_handle_amsdu(struct ath10k_htt *htt)
+ {
+ struct ath10k *ar = htt->ar;
+- static struct ieee80211_rx_status rx_status;
++ struct ieee80211_rx_status *rx_status = &htt->rx_status;
+ struct sk_buff_head amsdu;
+ int ret;
+
+@@ -1549,11 +1549,11 @@ static int ath10k_htt_rx_handle_amsdu(struct ath10k_htt *htt)
+ return ret;
+ }
+
+- ath10k_htt_rx_h_ppdu(ar, &amsdu, &rx_status, 0xffff);
++ ath10k_htt_rx_h_ppdu(ar, &amsdu, rx_status, 0xffff);
+ ath10k_htt_rx_h_unchain(ar, &amsdu, ret > 0);
+- ath10k_htt_rx_h_filter(ar, &amsdu, &rx_status);
+- ath10k_htt_rx_h_mpdu(ar, &amsdu, &rx_status);
+- ath10k_htt_rx_h_deliver(ar, &amsdu, &rx_status);
++ ath10k_htt_rx_h_filter(ar, &amsdu, rx_status);
++ ath10k_htt_rx_h_mpdu(ar, &amsdu, rx_status);
++ ath10k_htt_rx_h_deliver(ar, &amsdu, rx_status);
+
+ return 0;
+ }
+--
+cgit v0.12
+
projects / openwrt-github / .git / commitdiff