X-Git-Url: http://git.ozo.com/?a=blobdiff_plain;f=target%2Flinux%2Fifxmips%2Fpatches-2.6.28%2F010-mips_clocksource_init_war.patch;fp=target%2Flinux%2Fifxmips%2Fpatches-2.6.28%2F010-mips_clocksource_init_war.patch;h=0000000000000000000000000000000000000000;hb=4fea8d2283645d50dc58ab28036713f2e16e5082;hp=ac44c308fa850b0d485b615c34bf76c3edcbf276;hpb=9e0befc4f375fcf7886eac609ac82738c0e5129c;p=openwrt-10.03%2F.git

diff --git a/target/linux/ifxmips/patches-2.6.28/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.28/010-mips_clocksource_init_war.patch
deleted file mode 100644
index ac44c308f..000000000
--- a/target/linux/ifxmips/patches-2.6.28/010-mips_clocksource_init_war.patch
+++ /dev/null
@@ -1,33 +0,0 @@
---- a/arch/mips/kernel/cevt-r4k.c
-+++ b/arch/mips/kernel/cevt-r4k.c
-@@ -21,6 +21,22 @@
- 
- #ifndef CONFIG_MIPS_MT_SMTC
- 
-+/*
-+ * Compare interrupt can be routed and latched outside the core,
-+ * so a single execution hazard barrier may not be enough to give
-+ * it time to clear as seen in the Cause register.  4 time the
-+ * pipeline depth seems reasonably conservative, and empirically
-+ * works better in configurations with high CPU/bus clock ratios.
-+ */
-+
-+#define compare_change_hazard() \
-+	do { \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+		irq_disable_hazard(); \
-+	} while (0)
-+
- static int mips_next_event(unsigned long delta,
-                            struct clock_event_device *evt)
- {
-@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
- 	cnt = read_c0_count();
- 	cnt += delta;
- 	write_c0_compare(cnt);
-+	compare_change_hazard();
- 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
- 	return res;
- }