X-Git-Url: http://git.ozo.com/?a=blobdiff_plain;f=target%2Flinux%2Far71xx%2Ffiles%2Finclude%2Fasm-mips%2Fmach-ar71xx%2Far71xx.h;h=f68bfff19977dd68822db7b5e668cc7c0c5bccea;hb=4999d90052d4a00d74d17119f70f470588c5142d;hp=92e662e2ba23521eaed2ab968d50d46f41917a27;hpb=ad788429d14f135fd5947e865d2c800786296ebe;p=openwrt-10.03%2F.git

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 92e662e2b..f68bfff19 100644
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -92,6 +92,17 @@ extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
 
+enum ar71xx_soc_type {
+	AR71XX_SOC_UNKNOWN,
+	AR71XX_SOC_AR7130,
+	AR71XX_SOC_AR7141,
+	AR71XX_SOC_AR7161,
+	AR71XX_SOC_AR9130,
+	AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
 /*
  * PLL block
  */
@@ -196,18 +207,23 @@ extern void ar71xx_gpio_function_disable(u32 mask);
 /*
  * DDR_CTRL block
  */
-#define DDR_REG_PCI_WIN0	0x7c
-#define DDR_REG_PCI_WIN1	0x80
-#define DDR_REG_PCI_WIN2	0x84
-#define DDR_REG_PCI_WIN3	0x88
-#define DDR_REG_PCI_WIN4	0x8c
-#define DDR_REG_PCI_WIN5	0x90
-#define DDR_REG_PCI_WIN6	0x94
-#define DDR_REG_PCI_WIN7	0x98
-#define DDR_REG_FLUSH_GE0	0x9c
-#define DDR_REG_FLUSH_GE1	0xa0
-#define DDR_REG_FLUSH_USB	0xa4
-#define DDR_REG_FLUSH_PCI	0xa8
+#define AR71XX_DDR_REG_PCI_WIN0		0x7c
+#define AR71XX_DDR_REG_PCI_WIN1		0x80
+#define AR71XX_DDR_REG_PCI_WIN2		0x84
+#define AR71XX_DDR_REG_PCI_WIN3		0x88
+#define AR71XX_DDR_REG_PCI_WIN4		0x8c
+#define AR71XX_DDR_REG_PCI_WIN5		0x90
+#define AR71XX_DDR_REG_PCI_WIN6		0x94
+#define AR71XX_DDR_REG_PCI_WIN7		0x98
+#define AR71XX_DDR_REG_FLUSH_GE0	0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1	0xa0
+#define AR71XX_DDR_REG_FLUSH_USB	0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI	0xa8
+
+#define AR91XX_DDR_REG_FLUSH_GE0	0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1	0x80
+#define AR91XX_DDR_REG_FLUSH_USB	0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC	0x88
 
 #define PCI_WIN0_OFFS	0x10000000
 #define PCI_WIN1_OFFS	0x11000000
@@ -275,6 +291,13 @@ extern void ar71xx_ddr_flush(u32 reg);
 #define RESET_REG_PERFC1		0x34
 #define RESET_REG_REV_ID		0x90
 
+#define WDOG_CTRL_LAST_RESET		BIT(31)
+#define WDOG_CTRL_ACTION_MASK		3
+#define WDOG_CTRL_ACTION_NONE		0	/* no action */
+#define WDOG_CTRL_ACTION_GPI		1	/* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI		2	/* NMI */
+#define WDOG_CTRL_ACTION_FCR		3	/* full chip reset */
+
 #define MISC_INT_DMA			BIT(7)
 #define MISC_INT_OHCI			BIT(6)
 #define MISC_INT_PERFC			BIT(5)
@@ -314,6 +337,7 @@ extern void ar71xx_ddr_flush(u32 reg);
 #define REV_ID_CHIP_AR7141	0xa1
 #define REV_ID_CHIP_AR7161	0xa2
 #define REV_ID_CHIP_AR9130	0xb0
+#define REV_ID_CHIP_AR9132	0xb1
 
 #define REV_ID_REVISION_MASK	0x3
 #define REV_ID_REVISION_SHIFT	2