[ar7] update to 2.6.27 (#4122)

[openwrt-10.03/.git] / target / linux / ar7 / patches-2.6.27 / 100-board_support.patch

diff --git a/target/linux/ar7/patches-2.6.27/100-board_support.patch b/target/linux/ar7/patches-2.6.27/100-board_support.patch
new file mode 100644 (file)
index 0000000..2708f75
--- /dev/null
+++ b/target/linux/ar7/patches-2.6.27/100-board_support.patch
@@ -0,0 +1,86 @@
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -18,6 +18,24 @@ choice
+       prompt "System type"
+       default SGI_IP22
+ 
++config AR7
++      bool "Texas Instruments AR7"
++      select BOOT_ELF32
++      select DMA_NONCOHERENT
++      select CEVT_R4K
++      select CSRC_R4K
++      select IRQ_CPU
++      select NO_EXCEPT_FILL
++      select SWAP_IO_SPACE
++      select SYS_HAS_CPU_MIPS32_R1
++      select SYS_HAS_EARLY_PRINTK
++      select SYS_SUPPORTS_32BIT_KERNEL
++      select SYS_SUPPORTS_KGDB
++      select SYS_SUPPORTS_LITTLE_ENDIAN
++      select SYS_SUPPORTS_BIG_ENDIAN
++      select GENERIC_GPIO
++      select GENERIC_HARDIRQS_NO__DO_IRQ
++
+ config MACH_ALCHEMY
+       bool "Alchemy processor based machines"
+ 
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -1188,9 +1188,22 @@ void *set_except_vector(int n, void *add
+ 
+       exception_handlers[n] = handler;
+       if (n == 0 && cpu_has_divec) {
+-              *(u32 *)(ebase + 0x200) = 0x08000000 |
+-                                        (0x03ffffff & (handler >> 2));
+-              local_flush_icache_range(ebase + 0x200, ebase + 0x204);
++              if ((handler ^ (ebase + 4)) & 0xfc000000) {
++                      /* lui k0, 0x0000 */
++                      *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16);
++                      /* ori k0, 0x0000 */
++                      *(u32 *)(ebase + 0x204) =
++                                      0x375a0000 | (handler & 0xffff);
++                      /* jr k0 */
++                      *(u32 *)(ebase + 0x208) = 0x03400008;
++                      /* nop */
++                      *(u32 *)(ebase + 0x20C) = 0x00000000;
++                      flush_icache_range(ebase + 0x200, ebase + 0x210);
++              } else {
++                      *(u32 *)(ebase + 0x200) =
++                              0x08000000 | (0x03ffffff & (handler >> 2));
++                      flush_icache_range(ebase + 0x200, ebase + 0x204);
++              }
+       }
+       return (void *)old_handler;
+ }
+--- a/arch/mips/Makefile
++++ b/arch/mips/Makefile
+@@ -167,6 +167,13 @@ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/s
+ #
+ 
+ #
++# Texas Instruments AR7
++#
++core-$(CONFIG_AR7)            += arch/mips/ar7/
++cflags-$(CONFIG_AR7)          += -Iinclude/asm-mips/ar7
++load-$(CONFIG_AR7)            += 0xffffffff94100000
++
++#
+ # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
+ #
+ core-$(CONFIG_MACH_JAZZ)      += arch/mips/jazz/
+--- a/include/asm-mips/page.h
++++ b/include/asm-mips/page.h
+@@ -182,8 +182,10 @@ typedef struct { unsigned long pgprot; }
+ #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
+                                VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+ 
+-#define UNCAC_ADDR(addr)      ((addr) - PAGE_OFFSET + UNCAC_BASE)
+-#define CAC_ADDR(addr)                ((addr) - UNCAC_BASE + PAGE_OFFSET)
++#define UNCAC_ADDR(addr)      ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
++                               PHYS_OFFSET)
++#define CAC_ADDR(addr)                ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
++                               PHYS_OFFSET)
+ 
+ #include <asm-generic/memory_model.h>
+ #include <asm-generic/page.h>