/* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved. * Copyright (C) 2007 Felix Fietkau * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ /* FIXME: convert nasty volatile register derefs to readl/writel calls */ #include #include #include #include #include #include #include #include #include #include #define AMAZON_PCI_REG32( addr ) (*(volatile u32 *)(addr)) #ifndef AMAZON_PCI_MEM_BASE #define AMAZON_PCI_MEM_BASE 0xb2000000 #endif #define AMAZON_PCI_MEM_SIZE 0x00400000 #define AMAZON_PCI_IO_BASE 0xb2400000 #define AMAZON_PCI_IO_SIZE 0x00002000 #define AMAZON_PCI_CFG_BUSNUM_SHF 16 #define AMAZON_PCI_CFG_DEVNUM_SHF 11 #define AMAZON_PCI_CFG_FUNNUM_SHF 8 #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 static inline u32 amazon_r32(u32 addr) { u32 *ptr = (u32 *) addr; return __raw_readl(ptr); } static inline void amazon_w32(u32 addr, u32 val) { u32 *ptr = (u32 *) addr; __raw_writel(val, ptr); } static struct resource pci_io_resource = { .name = "io pci IO space", #if 0 .start = AMAZON_PCI_IO_BASE, .end = AMAZON_PCI_IO_BASE + AMAZON_PCI_IO_SIZE - 1, #endif .start = 0, .end = AMAZON_PCI_IO_SIZE - 1, .flags = IORESOURCE_IO }; static struct resource pci_mem_resource = { .name = "ext pci memory space", .start = AMAZON_PCI_MEM_BASE, .end = AMAZON_PCI_MEM_BASE + AMAZON_PCI_MEM_SIZE - 1, .flags = IORESOURCE_MEM }; static inline u32 amazon_pci_swap(u32 val) { #ifdef CONFIG_AMAZON_PCI_HW_SWAP return swab32(val); #else return val; #endif } static int amazon_pci_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) { unsigned long flags; u32 pci_addr; u32 val; int ret; /* Amazon support slot from 0 to 15 */ /* devfn 0 & 0x20 is itself */ if ((bus->number != 0) || (devfn == 0) || (devfn == 0x20)) return 1; pci_addr=AMAZON_PCI_CFG_BASE | bus->number << AMAZON_PCI_CFG_BUSNUM_SHF | devfn << AMAZON_PCI_CFG_FUNNUM_SHF | (where & ~0x3); local_irq_save(flags); if (access_type == PCI_ACCESS_WRITE) { val = amazon_pci_swap(*data); ret = put_dbe(val, (u32 *)pci_addr); } else { ret = get_dbe(val, (u32 *)pci_addr); *data = amazon_pci_swap(val); } amazon_w32(PCI_MODE, amazon_r32(PCI_MODE) & (~(1<> ((where & 3) << 3)) & 0xff; else if (size == 2) *val = (data >> ((where & 3) << 3)) & 0xffff; else *val = data; return PCIBIOS_SUCCESSFUL; } static int amazon_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { u32 data = 0; if (size == 4) { data = val; } else { if (amazon_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) return PCIBIOS_DEVICE_NOT_FOUND; if (size == 1) data = (data & ~(0xff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); else if (size == 2) data = (data & ~(0xffff << ((where & 3) << 3))) | (val << ((where & 3) << 3)); } if (amazon_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_SUCCESSFUL; } static struct pci_ops amazon_pci_ops = { amazon_pci_read, amazon_pci_write }; static struct pci_controller amazon_pci_controller = { .pci_ops = &amazon_pci_ops, .mem_resource = &pci_mem_resource, .io_resource = &pci_io_resource }; int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { switch (slot) { case 13: /* IDSEL = AD29 --> USB Host Controller */ return INT_NUM_IM2_IRL15; case 14: /* IDSEL = AD30 --> mini PCI connector */ return INT_NUM_IM2_IRL14; default: printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin); return 0; } } int pcibios_plat_dev_init(struct pci_dev *dev) { switch(dev->irq) { case INT_NUM_IM2_IRL15: /* * IDSEL = AD29 --> USB Host Controller * PCI_INTA/B/C--GPIO Port0.2--EXIN3 * IN/ALT0:1 ALT1:0 * PULL UP */ (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffb; (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 4; (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffb; (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 4; (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 4; //External Interrupt Node (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x6000; /* Low Level triggered */ (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x8; pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); break; case INT_NUM_IM2_IRL14: /* * IDSEL = AD30 --> mini PCI connector * PCI_INTA--GPIO Port0.1--EXIN2 * IN/ALT0:1 ALT1:0 * PULL UP */ (*AMAZON_GPIO_P0_DIR) = (*AMAZON_GPIO_P0_DIR) & 0xfffffffd; (*AMAZON_GPIO_P0_ALTSEL0) = (*AMAZON_GPIO_P0_ALTSEL0)| 2; (*AMAZON_GPIO_P0_ALTSEL1) = (*AMAZON_GPIO_P0_ALTSEL1)& 0xfffffffd; (*AMAZON_GPIO_P0_PUDSEL) = (*AMAZON_GPIO_P0_PUDSEL) | 2; (*AMAZON_GPIO_P0_PUDEN) = (*AMAZON_GPIO_P0_PUDEN) | 2; //External Interrupt Node (*AMAZON_ICU_EXTINTCR) = (*AMAZON_ICU_EXTINTCR)|0x600; (*AMAZON_ICU_IRNEN) = (*AMAZON_ICU_IRNEN)|0x4; pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); break; default: return 1; } return 0; } int __init amazon_pci_init(void) { u32 temp_buffer; #ifdef CONFIG_AMAZON_PCI_HW_SWAP AMAZON_PCI_REG32(IRM) = AMAZON_PCI_REG32(IRM) | (1<<27) | (1<<28); wmb(); #endif AMAZON_PCI_REG32(CLOCK_CONTROL) = AMAZON_PCI_REG32(CLOCK_CONTROL) | (1<