1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/of_platform.h>
5 #include <linux/clocksource.h>
6 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
10 #include <linux/reset.h>
11 #include <asm/mach-types.h>
12 #include <asm/mach/map.h>
13 #include <asm/mach/arch.h>
15 #include <mach/iomap.h>
16 #include <mach/hardware.h>
17 #include <mach/utils.h>
20 static struct map_desc ox820_io_desc[] __initdata = {
22 .virtual = (unsigned long)OXNAS_PERCPU_BASE_VA,
23 .pfn = __phys_to_pfn(OXNAS_PERCPU_BASE),
24 .length = OXNAS_PERCPU_SIZE,
28 .virtual = (unsigned long)OXNAS_SYSCRTL_BASE_VA,
29 .pfn = __phys_to_pfn(OXNAS_SYSCRTL_BASE),
30 .length = OXNAS_SYSCRTL_SIZE,
34 .virtual = (unsigned long)OXNAS_SECCRTL_BASE_VA,
35 .pfn = __phys_to_pfn(OXNAS_SECCRTL_BASE),
36 .length = OXNAS_SECCRTL_SIZE,
40 .virtual = (unsigned long)OXNAS_RPSA_BASE_VA,
41 .pfn = __phys_to_pfn(OXNAS_RPSA_BASE),
42 .length = OXNAS_RPSA_SIZE,
46 .virtual = (unsigned long)OXNAS_RPSC_BASE_VA,
47 .pfn = __phys_to_pfn(OXNAS_RPSC_BASE),
48 .length = OXNAS_RPSC_SIZE,
53 void __init ox820_map_common_io(void)
56 iotable_init(ox820_io_desc, ARRAY_SIZE(ox820_io_desc));
59 static void __init ox820_dt_init(void)
63 ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
67 pr_err("of_platform_populate failed: %d\n", ret);
73 static void __init ox820_timer_init(void)
76 clocksource_of_init();
79 void ox820_init_early(void)
84 void ox820_assert_system_reset(enum reboot_mode mode, const char *cmd)
88 /* Assert reset to cores as per power on defaults
89 * Don't touch the DDR interface as things will come to an impromptu stop
90 * NB Possibly should be asserting reset for PLLB, but there are timing
91 * concerns here according to the docs */
92 value = BIT(SYS_CTRL_RST_COPRO) |
93 BIT(SYS_CTRL_RST_USBHS) |
94 BIT(SYS_CTRL_RST_USBHSPHYA) |
95 BIT(SYS_CTRL_RST_MACA) |
96 BIT(SYS_CTRL_RST_PCIEA) |
97 BIT(SYS_CTRL_RST_SGDMA) |
98 BIT(SYS_CTRL_RST_CIPHER) |
99 BIT(SYS_CTRL_RST_SATA) |
100 BIT(SYS_CTRL_RST_SATA_LINK) |
101 BIT(SYS_CTRL_RST_SATA_PHY) |
102 BIT(SYS_CTRL_RST_PCIEPHY) |
103 BIT(SYS_CTRL_RST_STATIC) |
104 BIT(SYS_CTRL_RST_UART1) |
105 BIT(SYS_CTRL_RST_UART2) |
106 BIT(SYS_CTRL_RST_MISC) |
107 BIT(SYS_CTRL_RST_I2S) |
108 BIT(SYS_CTRL_RST_SD) |
109 BIT(SYS_CTRL_RST_MACB) |
110 BIT(SYS_CTRL_RST_PCIEB) |
111 BIT(SYS_CTRL_RST_VIDEO) |
112 BIT(SYS_CTRL_RST_USBHSPHYB) |
113 BIT(SYS_CTRL_RST_USBDEV);
115 writel(value, SYS_CTRL_RST_SET_CTRL);
117 /* Release reset to cores as per power on defaults */
118 writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
120 /* Disable clocks to cores as per power-on defaults - must leave DDR
121 * related clocks enabled otherwise we'll stop rather abruptly. */
123 BIT(SYS_CTRL_CLK_COPRO) |
124 BIT(SYS_CTRL_CLK_DMA) |
125 BIT(SYS_CTRL_CLK_CIPHER) |
126 BIT(SYS_CTRL_CLK_SD) |
127 BIT(SYS_CTRL_CLK_SATA) |
128 BIT(SYS_CTRL_CLK_I2S) |
129 BIT(SYS_CTRL_CLK_USBHS) |
130 BIT(SYS_CTRL_CLK_MAC) |
131 BIT(SYS_CTRL_CLK_PCIEA) |
132 BIT(SYS_CTRL_CLK_STATIC) |
133 BIT(SYS_CTRL_CLK_MACB) |
134 BIT(SYS_CTRL_CLK_PCIEB) |
135 BIT(SYS_CTRL_CLK_REF600) |
136 BIT(SYS_CTRL_CLK_USBDEV);
138 writel(value, SYS_CTRL_CLK_CLR_CTRL);
140 /* Enable clocks to cores as per power-on defaults */
142 /* Set sys-control pin mux'ing as per power-on defaults */
143 writel(0, SYS_CTRL_SECONDARY_SEL);
144 writel(0, SYS_CTRL_TERTIARY_SEL);
145 writel(0, SYS_CTRL_QUATERNARY_SEL);
146 writel(0, SYS_CTRL_DEBUG_SEL);
147 writel(0, SYS_CTRL_ALTERNATIVE_SEL);
148 writel(0, SYS_CTRL_PULLUP_SEL);
150 writel(0, SYS_CTRL_SECONDARY_SEL);
151 writel(0, SYS_CTRL_TERTIARY_SEL);
152 writel(0, SYS_CTRL_QUATERNARY_SEL);
153 writel(0, SYS_CTRL_DEBUG_SEL);
154 writel(0, SYS_CTRL_ALTERNATIVE_SEL);
155 writel(0, SYS_CTRL_PULLUP_SEL);
157 /* No need to save any state, as the ROM loader can determine whether
158 * reset is due to power cycling or programatic action, just hit the
159 * (self-clearing) CPU reset bit of the block reset register */
161 BIT(SYS_CTRL_RST_SCU) |
162 BIT(SYS_CTRL_RST_ARM0) |
163 BIT(SYS_CTRL_RST_ARM1);
165 writel(value, SYS_CTRL_RST_SET_CTRL);
168 static const char * const ox820_dt_board_compat[] = {
175 DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)")
176 .map_io = ox820_map_common_io,
177 .smp = smp_ops(ox820_smp_ops),
178 .init_early = ox820_init_early,
179 .init_time = ox820_timer_init,
180 .init_machine = ox820_dt_init,
181 .restart = ox820_assert_system_reset,
182 .dt_compat = ox820_dt_board_compat,